An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

Sohn, Kiwon; Mo, H. J.; Suh, Young-Joo; Byun, Hyun-Geun; Yoo, Hoi‐Jun

doi:10.1109/jssc.2006.870759

Cited by 5 publications

(8 citation statements)

References 14 publications

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“…In the subthreshold region, intra-die variation results in large delay variation and increases the worst-case offset voltage of the sense amplifier. Hence, extremely long delay buffer is required for strobe timing [12], incurring large area and performance penalty. In this work, we employ the footer transistor M0 instead of the strobe-delay method (Fig.…”

Section: B Dynamic Dcvsl Read Schemementioning

confidence: 99%

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Chang

Kim

Park

et al. 2009

IEEE J. Solid-State Circuits

398

205

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Abstract-Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable subthreshold operation. Hence, researchers have considered different configuration SRAMs for subthreshold operations having single-ended 8T or 10T bit-cells for improved stability. While these bit-cells improve SRAM stability in subthreshold region significantly, the single-ended sensing methods suffer from reduced bit-line swing due to bit-line leakage noise. In addition, efficient bit-interleaving in column may not be possible and hence, the multiple-bit soft errors can be a real issue. In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. The proposed bit-cell also provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise, thereby improving bitline swing.

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Section: B Dynamic Dcvsl Read Schemementioning

confidence: 99%

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Chang

Kim

Park

et al. 2009

IEEE J. Solid-State Circuits

398

205

View full text Add to dashboard Cite

show abstract

“…It showed the promising potential for the sensor-based feedback control system to be implemented in the real commercial products to further improve their runtime performance. Sohn et al proposed a sensor-based solution for SRAM to overcome the uncertainty and fluctuation of device parameters [26], [27]. These works show that the information gathered by on-chip sensors can be used to effectively improve the reliability and performance of different functional units, and it will come to practice as a powerful strategy for the next generation commercial products.…”

Section: Related Workmentioning

confidence: 99%

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuitlevel MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

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“…Tiny on-chip sensors can measure various run-time parameters, such as noise, temperature, switching activity, clock duty-cycle, and technology parameters [4,5,6,7,8]. Petrescu et al proposed a signal integrity architecture to monitor various on-chip physical parameters, especially voltage and temperature [4].…”

Section: Introductionmentioning

confidence: 99%

“…Poirier et al and McGowen et al described the control system on a 90-nm Itanium processor which utilizes on-chip sensors to measure power and temperature and modulates voltage and frequency to optimize performance [5,6]. Sohn et al proposed a sensor-based solution for SRAM to overcome the uncertainty and fluctuation of device parameters [7,8]. These works show that the information gathered by on-chip sensors can be used to effectively improve the reliability and performance of different functional units.…”

Section: Introductionmentioning

confidence: 99%

A case study of on-chip sensor network in multiprocessor system-on-chip

Wang

Huang

et al. 2009

Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at run time could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used and explained in our case study to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.12% performance improvement compared with the traditional stop-go method with 1.4% area overhead in an 8*8-core MPSoC in 45nm.

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An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

Cited by 5 publications

References 14 publications

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

A case study of on-chip sensor network in multiprocessor system-on-chip

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