An Active Pixel CMOS separable transform image sensor

Yu, Miao; Abbas, Adeel; Chakrabartty, Shantanu; Cauwenberghs, Gert

doi:10.1109/iscas.2009.5117997

Cited by 21 publications

(7 citation statements)

References 13 publications

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“…The x-axis represents the normalized standard deviation of the pixel offset σ e X . The theoretical curve based on (16) and the simulated curve based on direct modeling of the pixel offset match significantly better than the dark current curves do ( Figure 5). This is an expected result because the overall dark current error depends on the benchmark image content, while the pixel offset error is scene-independent.…”

Section: Offset Fixed Pattern Noisementioning

confidence: 81%

“…The separable-transform image sensor in [15] allows high readout speed and camera resolution but suffers from device mismatch effects in the analog-matrix generation as well as high readout noise. Another separable-transform imager [16] can perform CS; however, it is limited to very small pixel blocks. The most promising design proposed in [17] implements the first reported single-shot imaging CS acquisition that is suitable for video applications.…”

Section: Introductionmentioning

confidence: 99%

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Compressive image acquisition in modern CMOS IC design

Katic

Kamal

Schmid

et al. 2013

Circuit Theory & Apps

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SUMMARYCompressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well-established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non-idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs.

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Section: Offset Fixed Pattern Noisementioning

confidence: 81%

Section: Introductionmentioning

confidence: 99%

Compressive image acquisition in modern CMOS IC design

Katic

Kamal

Schmid

et al. 2013

Circuit Theory & Apps

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“…The APS and switched capacitor circuits are used in [67] to implement a separable transform imager. By adding one transistor and one capacitor to the three-transistor APS structure and using a switched capacitor circuit for each column, the random combination of the pixels for each column is achieved.…”

Section: Hardware Implementationmentioning

confidence: 99%

Compressive Sensing Image Sensors-Hardware Implementation

Dadkhah

Deen

Shirani

2013

Sensors

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The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

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“…In [28], a 3-transistor APS structure [29], one extra inpixel transistor and capacitor, and switched capacitor (SC) circuits were used to implement the CS coding during the integration time. The 3-transistor APS and SC circuits were also used in [30] to design a block-based implementation of CS without using extra in-pixel components.…”

Section: Introductionmentioning

confidence: 99%

CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

2015

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We have designed, fabricated and measured the performance of a linear and area-efficient implementation of the compressive sensing (CS) method in CMOS (complementary metal-oxide-semiconductor) image sensors. The use of an active pixel sensor (APS) with an integrator and in-pixel current switches are exploited to develop a compact implementation of CS encoding in analog domain. The intrinsic linearity of APS with integrator circuit guarantees the linearity of the CS encoding structure. The CS measurement process is performed for different blocks of the imager separately. This block-based implementation provides individual access to all the pixels from outside the array, resulting in a scalable design with relatively high fill-factor by using only two transistors in each pixel. The CS-CMOS image sensor is designed and fabricated in 130nm technology for 2×2, 4×4 and 16×16 arrays. The linearity of the extracted measurement is confirmed by the experimental results from 2 × 2 and 4 × 4 blocks. Also, the block read-out scheme and the scalability of the design is examined by fabricating a larger array of 4 × 4 blocks.

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An Active Pixel CMOS separable transform image sensor

Cited by 21 publications

References 13 publications

Compressive image acquisition in modern CMOS IC design

Compressive image acquisition in modern CMOS IC design

Compressive Sensing Image Sensors-Hardware Implementation

CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

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