CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

Dadkhah, Mohammadreza; Deen, M. Jamal; Shirani, Shahram

doi:10.1109/jsen.2015.2397874

Cited by 27 publications

(11 citation statements)

References 41 publications

(34 reference statements)

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“…Content may change prior to final publication. [15]. Inside of each pixel, the flip-flops are replaced by simple and more compact selectors.…”

Section: Rip Of Binary Matrices Produced By Pseudo Random Binary mentioning

confidence: 99%

“…If each pixel received two driving signals, it would be possible to use one of them to determine if the pixel took part in a compressed sample and, in case it did, use the other to select the sign of its contribution. Since recent CS-CIS examples [6][14] [15] have shown that as few as = 2√ bits of information are needed to generate binary measurement matrices on-chip, the amount of resources (number of transistors) needed to incorporate a ternary matrix would still be implementable in a CS-CIS design. Each coefficient of the resulting matrix would have a probability distribution of:…”

Section: Ternary Matrices Generated Using Class III Elementary Cmentioning

confidence: 99%

See 1 more Smart Citation

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

Trevisi¹,

Akbari²,

Trocan³

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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In this paper we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in compressive sensing CMOS image sensors (CS-CIS) are recursive pseudo-random binary matrices. We have proved that the restricted isometry property (RIP) of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random numbers generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behaviour that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a blockbased CS smoothed-projected Landweber (BCS-SPL) reconstruction algorithm. By means of single value decomposition (SVD) we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.Index Terms-CMOS image sensor architecture, compressive sensing, Landweber reconstruction, power spectral density, random binary matrix RIP proof, single value decomposition, ternary measurement matrix.

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“…Content may change prior to final publication. [15]. Inside of each pixel, the flip-flops are replaced by simple and more compact selectors.…”

Section: Rip Of Binary Matrices Produced By Pseudo Random Binary mentioning

confidence: 99%

Section: Ternary Matrices Generated Using Class III Elementary Cmentioning

confidence: 99%

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

Trevisi¹,

Akbari²,

Trocan³

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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show abstract

“…Noting that data reduction during the CS measurement does not completely equal to signal compression yet, though these measurements can be transmitted directly [5,6], a large bandwidth is still needed. To further reduce load of the transmitter, CS-CIS needs to be cooperated with a compressor to generate a compressed bitstream.…”

Section: Introductionmentioning

confidence: 99%

Measurement Coding Framework with Adjacent Pixels Based Measurement Matrix for Compressively Sensed Images

Wan

Zhou

Huang

et al. 2021

ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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To further compress measurements, the output of block-based compressed sensing, this work presents a measurement coding framework using measurement-domain intra prediction. In the framework, a deterministic measurement matrix based on the correlation of adjacent pixels (APMM) is proposed to embed the pixel-domain boundary information of each block to the measurement domain. By adopting APMM, the pixeldomain information can be efficiently used for measurementdomain intra prediction. To avoid the interference of pixels that are far apart and achieve a high prediction accuracy, we employ boundary measurements of neighboring blocks as reference for prediction. Finally, the residuals between measurements and predictions are processed by quantization and Huffman coding to generate a coded bit sequence for transmitting. Compared to the state-of-the-art, this work achieves a 24% decrease in bitrate and a 1.68dB increase in PSNR on average.

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“…So, column level ADC should be small in size. In CIS a scene is focused by a lens through an array of pixels on to image sensor which converts light into electrical signal [6]. Each pixel consists of one photodiode to sense the light and some transistor.…”

Section: Introductionmentioning

confidence: 99%

Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology

Yadav¹,

Mehra²,

Sehgal³

2016

IOSR

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An integrating type ADC is the most commonly used column level ADC for its simple architecture and small surface area. 12-bit Dual slope ADC is developed which has less complexity in design. This architecture has basic advantage that it eliminates the dependence of the conversion on the linearity and accuracy of the slope. The main block of this circuit is opamp. Two stage opamp is developed which has gain of 78dB. Dual slope integrator is designed which has one resistance in feed forward path and one feedback capacitance with opamp circuit. This dual slope column level ADC minimizes the conversion time. CMOS process is used because it provides high integration capabilities. This column level dual slope ADC is implemented using 180nm technology.

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CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

Cited by 27 publications

References 41 publications

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

Measurement Coding Framework with Adjacent Pixels Based Measurement Matrix for Compressively Sensed Images

Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology

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