The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.
We have designed, fabricated and measured the performance of a linear and area-efficient implementation of the compressive sensing (CS) method in CMOS (complementary metal-oxide-semiconductor) image sensors. The use of an active pixel sensor (APS) with an integrator and in-pixel current switches are exploited to develop a compact implementation of CS encoding in analog domain. The intrinsic linearity of APS with integrator circuit guarantees the linearity of the CS encoding structure. The CS measurement process is performed for different blocks of the imager separately. This block-based implementation provides individual access to all the pixels from outside the array, resulting in a scalable design with relatively high fill-factor by using only two transistors in each pixel. The CS-CMOS image sensor is designed and fabricated in 130nm technology for 2×2, 4×4 and 16×16 arrays. The linearity of the extracted measurement is confirmed by the experimental results from 2 × 2 and 4 × 4 blocks. Also, the block read-out scheme and the scalability of the design is examined by fabricating a larger array of 4 × 4 blocks.
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