An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Abstract

distortion in clock, timing margin is reduced by twice the amount of Inversion the duty-cycle distortion. The duty-cycle distortion is reduced using a duty-cycle corrector (DCC), however, the correction is limited by Jeong-Don Ihm, Seung-Jun Bae, Kwang-ll Park, Ho-Young Song, the offset of the duty cycle detector (DCD) and the jitter caused by hoi,clock signals whose duty cycle is corrected independently. When the Youn-WinPakKi, Oku-KooPark, Sen-MioYngKi, Jin-ongJi Jhoi, duty cycles of CLK and CLKb are a and b, respectively, the output Young-Wook Kimn, Hllyun-Kyu Lee, Sung-Hoon Kim, Seong-Jin Jang, dLuty of the phase interpolator is reduced to the average value of a Young-Hyun Jun, Soo-in Cho and 1-b. The low-frequency jitter caused by control voltage fluctuation in the duty-cycle detector is also reduced by the interpolation of Samsung Electronics, Hwasung, Korea CLK rising shape and CLKb falling shape whose jitter is opposite. Figure 27.4.3(b) shows the duty cycle of the output clock according The 3D graphics application demanLds a low-cost anLd high-banLdto the offsets of two DCDs. Usually two DCD offsets have the same width DRAM, which is implemented by extending the number of polarities because two DCDs are very close, and the duty distortion single-ended I/Os. However, the DRAM suffers from the bottlenecks of output clock is treduced of parallel single-ended signaling, such as simultaneous switching noise (SSN) [1], crosstalk, reference-voltage (V,,f) noise, and deter-Ron tuning is incorporated in GDDR4 DRAM to have higher noise ministic jitter due to inter-symbol interference (ISI) and duty-cylce margin at receiver. Ron tuning is implemented by adding a user-supdistortion. To increase the speed of parallel single-ended signaling, plied R,, offset value to the auto-calibrated Ron value [6] shown in we implement an 80nm 32b 512Mb GDDR4 DRAM with a low- Fig. 27.4.4(a). Ro tuning of the OCD and ODT, is similar to V, calpower and low-noise data bus inversion (DBI) scheme [2] with an ibration. If Vr,, is away from the optimum level, through R0,, tuning, analog majority voter that is insensitive to mismatch, a dual dutythe crossing point of a signal is tuned to Vl., level. Furthermore, Roll cycle corrector (DCC) to average DCC error, and a tunable off-chip tuning cancels out the offset value of OCD and ODT due to PVT driver (OCD) and on-die termination (ODT) [2] to obtain an effect variation. Figure 27.4.4(b) shows the optimum Ron value with the similar to V,.,, calibration with minimal overhead. maximum aperture window. This simulation result shows that R,, tuning for V, optimization is more effective than impedance match-DBI DC [3], shown in Fig. 27.4.1, restricts the number of zeros in lag between channel and termination in a short channel. Direct V,.,f parallel data to a maximum of four. DBI AC [4], also shown in Fig. caliblration requires extra area overhead, but R tuning is easily 27.4.1, restricts the number of transitions between previous and merged to the Rn auto-calibration circuit.on present data to a...

Improving cache lifetime reliability at ultra-low voltages

“…The number of logic gates and delay for this voter increases with an increase in number of inputs. Alternatively, one could use majority voter implementation based on a voltage sense amplifier (SA) [10,20]. A voltage SA evaluates the voltage difference between a pair of bitlines which are discharged by two groups of complemented logic.…”

Challenges and solutions for next generation main memory systems

“…To save further power consumption, NGS can apply a data bus inversion (DBI) coding technique, which is commonly used for the GDDR system [5]. Since steady-state current is only generated during the transmission of a 'high' value, the data bit pattern is inverted whenever more than half the transmitted data bits would be 'high' at any given time.…”

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

“…5(c), where the signal data pattern is set to excite the worst case crosstalk noise and ISI in the system during the PDN and channel co-simulation. GDDR4 systems support a special encoding scheme for the DQ channel called DBI DC (data bus inversion) to reduce supply noise during SSO events [1]. Since steady-state current is only generated during the transmission of a 'low' value, the DQ bit pattern is inverted whenever more than half the transmitted DQ bits would be 'low' at any given time.…”

“…The data rate of current GDDR3/4 systems is expected to move from 2Gbps to 4Gbps in the near future [1]. At such high data rates, SSO noise introduced by output drivers becomes the major bottleneck in designing memory channels*.…”