Improving cache lifetime reliability at ultra-low voltages

Chishti, Zeshan; Alameldeen, Alaa R.; Wilkerson, Chris; Wu, Wei; Lu, Shih-Lien

doi:10.1145/1669112.1669126

Cited by 145 publications

(124 citation statements)

References 31 publications

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“…Many previous papers have proposed the use of error-correcting codes (ECC) to improve cache reliability [9][14] [26]. Kim, et al [14], proposed two-dimensional ECC to correct multi-bit errors.…”

Section: Related Workmentioning

confidence: 99%

“…2D-ECC is tailored towards clustered bit defects and is less effective in dealing with high rates of random defects. Chishti, et al [9], proposed multiple-bit segmented ECC (MS-ECC) at fine sub-cache line granularities to tolerate high failure rates. MS-ECC sacrifices a large portion of the cache (25-50%) to store ECC check bits for the rest of the lines, which leads to performance loss during the lowvoltage mode.…”

Section: Related Workmentioning

confidence: 99%

“…The tag and data arrays are logically organized similar to traditional set-associative caches. Tags in this setup occupy only a small fraction (~10%) of the cache area and are assumed to be protected by either upsized cells or SECDED as proposed in [9] and [27]. Each cache line has an associated SECDED ECC field which contains check bits (of length l SECDED ) to correct one and detect two errors in the line.…”

Section: Cache Organizationmentioning

confidence: 99%

“…Prior work has explored techniques to enable ultra-low voltage cache operation in the context of high memory cell failure rates [1][2] [9][22] [27]. At such voltages, there is a high probability that one or more cache lines will exhibit multi-bit failures.…”

Section: Introductionmentioning

confidence: 99%

“…Our solution, variable-strength ECC (VS-ECC), allocates singleerror correcting, double-error detecting (SECDED) ECC to all cache lines, while reserving a few more bits per cache set to one or more lines that can exhibit multi-bit failures. The minimum SECDED protection allocated to all lines ensures that our design can recover from all single-bit non-persistent failures (e.g., due to soft errors or erratic failures [9]). Since SECDED is a standard feature in many existing cache designs [5] [23], the area overhead of VS-ECC is limited to the additional bits and logic needed to store and process the strong multi-bit ECC.…”

Section: Introductionmentioning

confidence: 99%

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Energy-efficient cache design using variable-strength error-correcting codes

Alameldeen

Wagner

Chishti

et al. 2011

SIGARCH Comput. Archit. News

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Voltage scaling is one of the most effective mechanisms to improve microprocessors" energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for the whole processor. We observe that most cache lines exhibit zero or one failures at low voltages. However, a few lines, especially in large caches, exhibit multi-bit failures and increase Vccmin. Previous solutions either significantly reduce cache capacity to enable uniform error correction across all lines, or significantly increase latency and bandwidth overheads when amortizing the cost of error-correcting codes (ECC) over large lines.In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. A small number of lines with multi-bit failures use a strong multi-bit ECC that requires some additional area and latency. We present a novel dynamic cache characterization mechanism to determine which lines will exhibit multi-bit failures. In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. Compared to prior multi-bit-correcting proposals, VS-ECC significantly reduces power and energy, avoids significant reductions in cache capacity, incurs little area overhead, and avoids large increases in latency and bandwidth.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%