An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Vangal, Sriram; Howard, Jason D.; Ruhl, G.; Dighe, Saurabh; Wilson, H.; Tschanz, James; Finan, D.; Iyer, Prakash; Singh, A.; Jacob, Tiju; Jain, Shailendra; Venkataraman, S.; Hoskote, Yatin; Borkar, Nitin

doi:10.1109/isscc.2007.373606

Cited by 451 publications

(262 citation statements)

References 5 publications

Supporting

Mentioning

258

Contrasting

Unclassified

Order By: Relevance

“…• NoC: In [18], Intel demonstrates the feasibility of packing 80 tile processors on a single chip by introducing a 275 mm 2 network-on-a-chip (NoC) architecture where each tile processor is arranged as a 10 × 8 2D array of floatingpoint cores and packet-switched routers, operating at 4 GHz. The design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors and body-bias techniques.…”

Section: Parallel Processing Has Become Mainstreammentioning

confidence: 99%

Invasive Computing: An Overview

Teich

Henkel²,

Herkersdorf³

et al. 2010

Multiprocessor System-on-Chip

103

View full text Add to dashboard Cite

A novel paradigm for designing and programming future parallel computing systems called invasive computing is proposed. The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to neighbour processors in a phase called invasion, then to execute portions of code of high parallelism degree in parallel based on the available invasible region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. In order to support this idea of self-adaptive and resource-aware programming, not only new programming concepts, languages, compilers and operating systems are necessary but also revolutionary architectural changes in the design of MPSoCs (Multi-Processor Systems-on-a-Chip) must be provided so to efficiently support invasion, infection and retreat operations involving concepts for dynamic processor, interconnect and memory reconfiguration. This contribution reveals the main ideas, potential benefits, and challenges for supporting invasive computing at the architectural, programming and compiler level in the future. It serves to give an overview of required research topics rather than being able to present mature solutions yet.

show abstract

Section: Parallel Processing Has Become Mainstreammentioning

confidence: 99%

Invasive Computing: An Overview

Teich

Henkel²,

Herkersdorf³

et al. 2010

Multiprocessor System-on-Chip

103

View full text Add to dashboard Cite

show abstract

“…In 2007, Intel designed, fabricated, and tested a large chip having 80 cores interconnected by a NoC. 3 An important issue is how to design NoCs that can be synthesized and optimized. Today, new design flows and tools (as well as emerging start-up companies) make it possible to implement NoCs starting from high-level specifications and to tailor them to the required applications, thus providing higher performance and lower power consumption ( Figure 1).…”

Section: Features and Challenges Of Socsmentioning

confidence: 99%

Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow

Micheli

2008

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

“…It is expected that devices with hundreds of cores interconnected by a NoC [6] can be designed and will become available in the coming years [10]. We expect that, due to energy and performance constraints, these cores will be reconfigurable and heterogeneous.…”

Section: A Streaming Applications and Mpsocsmentioning

confidence: 99%

Mapping streaming applications on a reconfigurable MPSoC platform at run-time

Hölzenspies

Smit

Kuper

2007

2007 International Symposium on System-on-Chip

View full text Add to dashboard Cite

-In this paper we present a method for mapping streaming applications, with real-time requirements, onto a reconfigurable MPSoC. In this method, the performance of the hardware architecture (the reconfigurable Processing Element, the Network Interface and the Network-on-Chip) is integrated in the performance models of the applications. In this way the performance of the mapped application can be determined at runtime. A predictable NoC (guaranteed bandwidth and bounded latency), a predictable Network Interface and a predictable Processing Element are key requirements for our approach.

show abstract

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Cited by 451 publications

References 5 publications

Invasive Computing: An Overview

Invasive Computing: An Overview

Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow

Mapping streaming applications on a reconfigurable MPSoC platform at run-time

Contact Info

Product

Resources

About