Amorphous Silicon Carbide/Crystalline Silicon Heterojunction Solar Cells: A Comprehensive Study of the Photocarrier Collection

Abstract

We have studied the current–voltage (I–V) characteristics of p+ a-SiC:H/n c-Si heterojunction solar cells at different conditions. Under standard test conditions (300 K, 100 mW/cm2, AM1.5) these cells show normal I–V characteristics with a high fill factor (FF = 0.73) and a relatively high efficiency for their simple structure (η≈13%). However, below room temperature and at illumination levels above 10 mW/cm2 they exhibit an S-shaped I–V curve and a low fill factor. Simulation studies revealed that this effect is caused by the valence band discontinuity at the amorphous/crystalline interface which hinders at low temperatures the collection of photogenerated holes at the front contact. At low temperatures a high hole accumulation at the interface combined with extra trapping of holes inside the p+ a-SiC:H layer causes a shift of the depletion region, from the c-Si into the p+ a-SiC:H. This leads to an enhanced recombination inside the c-Si depletion region causing a significant current loss (S-shape). Tunnelling through the valence band spike can reduce these effects. For lower doped p a-SiC:H layers (E act>0.4 eV) this S-shape can even occur at room temperature.

High-efficiency Silicon Heterojunction Solar Cells: A Review

“…For SHJ devices, such films should not jeopardize surface passivation and emitter formation. Tested alternatives to replace the a-Si:H stacks are (microcrystalline) silicon oxides [136,137,182,183] and carbides [148,[184][185][186]. Microcrystalline silicon has a lower but indirect bandgap and features a higher doping efficiency, making it an attractive material for emitter [52,[187][188][189][190] and BSF formation [189,[191][192][193] as well.…”

Defect states on the surfaces of a P-type c-Si wafer and how they control the performance of a double heterojunction solar cell

“…Hence the DOS model may be used for c-Si, provided that the mid gap DOS, to be used as an input parameter, is adjusted to yield a minority carrier lifetime that corresponds to the measured value. A DOS model was also used by van Cleef et al [8] to simulate the c-Si parts of their HIT cells. Using the DOS model, the lifetime of the minority carriers inside the P-c-Si wafer may be estimated using the formula:…”

“…While Sanyo has focused on P-a-Si:H/Nc-Si heterojunction (HJ) structures [1][2][3], European and US groups have studied HIT solar cells on both P-type and N-type substrates [4][5][6][7], and have obtained maximum efficiencies on P-type substrates between 17% and 18% [4,7]. Computer modeling of both types of HIT structures has also been carried out [8][9][10][11].…”

Amorphous silicon oxide window layers for high-efficiency silicon heterojunction solar cells

“…This improvement confirms earlier findings for wide-bandgap a-SiC:H buffer layers. 50 Due to a more favorable (efficiency) temperature coefficient b $ À0.1%/ C (compared to À0.3%/ C for the reference) in the investigated temperature range, the cell with an implemented oxide buffer layer shows an efficiency which, at high temperatures-those closer to real working conditions in the field-is superior to the standard cell design (Fig. 9).…”