We have studied the current–voltage (I–V) characteristics of p+ a-SiC:H/n c-Si heterojunction solar cells at different conditions. Under standard test conditions (300 K, 100 mW/cm2, AM1.5) these cells show normal I–V characteristics with a high fill factor (FF = 0.73) and a relatively high efficiency for their simple structure (η≈13%). However, below room temperature and at illumination levels above 10 mW/cm2 they exhibit an S-shaped I–V curve and a low fill factor. Simulation studies revealed that this effect is caused by the valence band discontinuity at the amorphous/crystalline interface which hinders at low temperatures the collection of photogenerated holes at the front contact. At low temperatures a high hole accumulation at the interface combined with extra trapping of holes inside the p+ a-SiC:H layer causes a shift of the depletion region, from the c-Si into the p+ a-SiC:H. This leads to an enhanced recombination inside the c-Si depletion region causing a significant current loss (S-shape). Tunnelling through the valence band spike can reduce these effects. For lower doped p a-SiC:H layers (E act>0.4 eV) this S-shape can even occur at room temperature.

We used the internal photoemission (IPE) technique to accurately determine the valence and conduction band offsets at the a-SiC:H/c-Si interface and investigated with numerical simulations their effects on the photocarrier collection in p+ a-SiC:H/n c-Si heterojunction solar cells. The valence and conduction band discontinuities were found to be 0.60 and 0.55 eV, respectively. However, despite the large barrier at the valence band edge, 30 nm p+ a-SiC:H/n c-Si heterojunction solar cells show no collection problems due to blocking of holes (FF=0.73). Combined IPE measurements and simulation results indicate that tunneling of holes through this barrier at the valence band edge can explain the unhindered collection.

We have studied by Raman spectroscopy and electro-optical characterization the properties of thin boron doped microcrystalline silicon layers deposited by plasma enhanced chemical vapor deposition ͑PECVD͒ on crystalline silicon wafers and on amorphous silicon buffer layers. Thin 20-30 nm p ϩ c-Si:H layers with a considerably large crystalline volume fraction (ϳ22%) and good window properties were deposited on crystalline silicon under moderate PECVD conditions. The performance of heterojunction solar cells incorporating such window layers were critically dependent on the interface quality and the type of buffer layer used. A large improvement of open circuit voltage is observed in these solar cells when a thin 2-3 nm wide band-gap buffer layer of intrinsic a-Si:H deposited at low temperature (ϳ100°C) is inserted between the microcrystalline and crystalline silicon ͓complete solar cell configuration: Al/(n)c-Si/buffer/p ϩ c-Si:H/ITO/Ag͔͒. Detailed modeling studies showed that the wide band-gap a-Si:H buffer layer is able to prevent electron backdiffusion into the p ϩ c-Si:H layer due to the discontinuity in the conduction band at the amorphous-crystalline silicon interface, thereby reducing the high recombination losses in the microcrystalline layer. At the same time, the discontinuity in the valence band is not limiting the hole exit to the front contact and does not deteriorate the solar cell performance. The defect density inside the crystalline silicon close to the amorphous-crystalline interface has a strong effect on the operation of the cell. An extra atomic hydrogen passivation treatment prior to buffer layer deposition, in order to reduce the number of these defects, did further enhance the values of V oc and fill factor, resulting in an efficiency of 12.2% for a cell without a back surface field and texturization.

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In the present paper we show results of dark current-voltage measurements performed on p+ a- SiC:H/n c-Si heterojunction diodes at various temperatures (100–400K). We investigated the voltage derivative of these J-V curves in order to the distinguish possible current transport mechanisms. It was found that for low temperatures (<300K), the current is determined by recombination of carriers in the crystalline silicon, whereas at high temperature (>300 K), by a tunnelling mechanism. At room temperature, both mechanisms contribute to the current. By using an equivalent circuit model and detailed numerical simulations we have interpreted our experimental characteristics. The simulations done at room temperature, show that at low forward bias voltage the current is controlled by recombination in the crystalline silicon and that at high forward bias voltage by a combination of multi-step tunnelling and a-SiC:H series resistance. For interface state densities equal to or higher than 1012 cm−2, the recombination was found to be dominated by the states at the amorphous-crystalline silicon interface.