We investigate the retention reliability of a 51-nmnode 16-GB NAND Flash cell transistor comprising SiO 2 /Al x O y / SiO 2 inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse V TH shift at 200 • C 2-h bake and 53% improved V TH shift after one week at 25 • C, when compared to the case of ONO IPD.Index Terms-High-k dielectric, inter-poly dielectric (IPD), NAND Flash memory, retention reliability.