Advanced backside failure analysis in 65nm CMOS technology

Bianic, S.; Allemand, Stéphanie; Kerrosa, Grégory; Scafidi, P.; Renard, Didier

doi:10.1016/j.microrel.2007.07.076

Cited by 4 publications

(3 citation statements)

References 2 publications

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“…For this reason, their detection and localization is a wellknown procedure used in failure analysis or design debugging [3,4], which can be based on microelectronic thermometric techniques [3]. However, in present-day complementary metal-oxide semiconductor (CMOS) technologies, monitoring the temperature of the chip surface with off-chip techniques is a challenging task: surface temperature is strongly attenuated by several metal layers (up to thirteen levels [5]) placed above the silicon surface. Moreover, in these technologies, there is a clear requirement for hot spot localization in terms of micronic and submicronic spatial resolution because the dimensions of the devices shrink and integration density increases [5].…”

Section: Introductionmentioning

confidence: 99%

Laser beam deflection-based perimeter scanning of integrated circuits for local overheating location

Perpiñà

Jordà

Altet

et al. 2008

J. Phys. D: Appl. Phys.

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In integrated circuits, local overheating (hot spots) can be detected by monitoring the temperature gradients present in the silicon substrate at a given depth, laterally accessing the die with an infra-red laser beam probe. The sensed magnitude is the laser beam deflection, which is proportional to the temperature gradients found along the beam trajectory (mirage effect). Biasing the devices with periodic electrical functions allows employing lock-in detection strategies (noise immunity) and thermally isolating the analysed chip substrate thermal behaviour from the external boundary conditions by setting the excitation frequency (control of the thermal energy penetration depth). Measuring the first harmonic of the deflection signal components (vertical and horizontal) allows performing a fast and accurate location of devices, interconnects or circuits dissipating relatively high power levels without any calibration procedure. It has been concluded that the horizontal component of the beam deflection provides a higher spatial resolution than the vertical one when measurements are performed beyond the thermal energy penetration depth.

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Section: Introductionmentioning

confidence: 99%

Laser beam deflection-based perimeter scanning of integrated circuits for local overheating location

Perpiñà

Jordà

Altet

et al. 2008

J. Phys. D: Appl. Phys.

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show abstract

“…Traditionally, off-chip temperature measurement set-ups have been used to detect unexpected hot spots within digital circuits [ 2 , 3 , 4 , 5 ]. Hot spots might appear either due to the presence of a defect in the circuit structure [ 6 , 7 , 8 , 9 ] or by a nonuniform power dissipation on the die surface, which is a common situation in microprocessors [ 4 , 10 ]. In complex digital systems, such as microprocessors, temperature sensors are built-in within the same silicon die in order to ensure reliable system performance, i.e., they perform power-temperature monitoring to control the activation of cooling systems, to modulate microprocessor supply voltage or clock frequency, or to assert if the workload of a specific microprocessor block can be increased or should be reduced to avoid nonuniform power distributions [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 ].…”

Section: Introductionmentioning

confidence: 99%

BPF-Based Thermal Sensor Circuit for On-Chip Testing of RF Circuits

Altet

Barajas

Mateo

et al. 2021

Sensors

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A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metal-oxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA’s output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.

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“…The growing demand for high spatial resolution in optical inspection for failure analysis of semiconductor integrated circuits (ICs) has aroused interest in employing aplanatic solid immersions lenses (aSILs) [1][2][3][4][5][6][7]. In such applications, aSILs are placed in intimate mechanical contact with the polished back-side of an IC chip, hence transforming the silicon substrate into a high refractive index immersion medium (n Si = ~3.5) for high numerical aperture (NA) sub-surface imaging.…”

Section: Introductionmentioning

confidence: 99%

Evanescent waves in high numerical aperture aplanatic solid immersion microscopy: Effects of forbidden light on subsurface imaging

Yurt¹,

Uyar²,

Cilingiroglu³

et al. 2014

Opt. Express

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The collection of light at very high numerical aperture allows detection of evanescent waves above the critical angle of total internal reflection in solid immersion lens microscopy. We investigate the effect of such evanescent modes, so-called forbidden light, on the far-field imaging properties of an aplanatic solid immersion microscope by developing a dyadic Green's function formalism in the context of subsurface semiconductor integrated circuit imaging. We demonstrate that the collection of forbidden light allows for sub-diffraction spatial resolution and substantial enhancement of photon collection efficiency albeit inducing wave-front discontinuities and aberrations.

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Advanced backside failure analysis in 65nm CMOS technology

Cited by 4 publications

References 2 publications

Laser beam deflection-based perimeter scanning of integrated circuits for local overheating location

Laser beam deflection-based perimeter scanning of integrated circuits for local overheating location

BPF-Based Thermal Sensor Circuit for On-Chip Testing of RF Circuits

Evanescent waves in high numerical aperture aplanatic solid immersion microscopy: Effects of forbidden light on subsurface imaging

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