Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation

A new test structure which can provide voltage to the very narrow source/drain region between adjacent gates by drawing out the source/drain silicide layer has been developed. By using the test structure, the dependence of the gate-drain capacitance (Cgd) on the gate-gate space (Lsp) has been successfully measured until the minimum gate pitch where no contact can be placed. Decrease of Cgd with respect to the decrease of Lsp has been observed and its main cause is identified as the decrease of the gate-drain overlap length.

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“…From Lsp_ref to minimum gate pitch, Lov shrinks by 2.8nm. The shrink is opposite to the expansion of Lov observed in [2].…”

Section: Step 3: Extraction Of Lov@(lsp=x)mentioning

confidence: 57%

“…As for Cov, it was reported that overlap length (i.e. Cov) increases with respect to the decrease of the gate-gate space [2]. On the other hand, CinF is expected to be invariant with respect to the gate-gate space as long as the source/drain junction depth is kept constant.…”

Section: Lsp1mentioning

confidence: 99%

Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure

Naruta

Kumashiro

2013

2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)

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“…The stress effects affect model parameters such as the effective mobility µ ef f , the velocity saturation V sat and the threshold voltage V th [17], [18], [19]. To reflect the influence of SA ef f and SB ef f , the parameter "α" is defined as follows:…”

Section: Stress Effect Parameter Computation 1) the Stress Effectsmentioning

confidence: 99%

A Python-based layout-aware analog design methodology for nanometric technologies

Youssef

Javid

Dupuis

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

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“…Tsuno et al in [8] discussed the contribution of the STIrelated parameters to device behaviors through measurement. Although the authors did not propose a new device model, their results showed that a device model without considering the STIW could not describe the characteristics of MOSFET accurately.…”

Section: The Simulation Of Sti Stressmentioning

confidence: 99%

Modeling of layout-dependent STI stress in 65nm Technology

Xue

Deng

et al. 2009

2009 IEEE 8th International Conference on ASIC

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In this work, we investigate the impact oflayout shapes on STI stress. Based on a stress simulator developed by us, we propose analytical models to correlate the STI stress and the layout parameters. Our model is validated by data collectedfrom a commercial 65nm process. The experimental results prove that the device characteristics predicted by our model closely match the measured data.Process simulators such as Taurus provide results with a high accuracy. However, they actually cannot consider the distribution of the STI stress of 2-D layout. Accordingly, we develop a new stress simulation tool [11], which is calibrated by Taurus simulation results on simple layout shapes. Using a finite element method, our stress simulator considers major stress sources, such as thermal mismatch, intrinsic stress, growth of materials and viscoelasticity, to perform highfidelity simulation of the STI stress. Fig. 2 shows a small Fi~. 1. Layout parameters related to STI stress stress distribution can be used to calibrate our stress simulator. With the stress simulator, the relation between the STI stress distribution and layout parameters can be studied in detail. Then we provide analytical models that could capture the impact of STI stress induced by arbitrary layout shapes. Finally we validate our model by applying it to analyze the subthreshold leakage current in 65nm technology.

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Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation

Cited by 50 publications

References 5 publications

Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure

Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure

A Python-based layout-aware analog design methodology for nanometric technologies

Modeling of layout-dependent STI stress in 65nm Technology

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