Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems

Abstract

One major advantage of reconfigurable computing systems is their ability to reconfigure hardware at runtime. In this paper, we study the feasibility of achieving energy efficiency in reconfigurable computing systems (e.g., FPGAs) through runtime partial reconfiguration (PR) techniques. In the ideal scenario, we use a hardware accelerator to accelerate certain parts of the program execution; when the accelerator is not active, we use partial reconfiguration to unload it to reduce power consumption. Since the reconfiguration process may introduce a high energy overhead, it is unclear whether this approach is efficient. To approach this problem, we first analytically identify the conditions under which partial reconfiguration can reduce energy consumption. Our results indicate that the key to reduce partial reconfiguration energy overhead is to minimize the time overhead of the reconfiguration process. Based on this analysis, we design and implement a fast reconfiguration engine that achieves close-to-ideal throughput on Xilinx Virtex-4 FPGAs. Our fast reconfiguration engine utilizes a master-slave DMA pair to stream data between the SRAM and the Internal Configuration Access Port (ICAP). We experimentally verify our proposed solutions and compare our design to existing energy reduction techniques, such as clock gating. The results of our study show that by using partial reconfiguration to eliminate the power consumption of the accelerator when it is inactive, we can accelerate program execution and at the same time reduce the overall energy consumption by half.

Formalization of the concept of adaptive tasks mapping in the reconfigurable computers on FPGA

“…Secondly, this allows to extend significantly the functional capabilities of the reconfigurable computer systems based on FPGA and to implement the complex computational structures on the limited chip area without huge cost increase [14]. The opportunity of reducing energy consumption based on using PDR technology is also actual [13,15,16].…”

“…In [15], the heuristic task mapping algorithm, which generates the minimized task assignment taking into account the overloading, the task of overheads minimization, the priorities and relations between the tasks is proposed. In [13], the scheme of the configuration data caching for overheads reducing is described. The proposed approach is based on the use of FPGA inner memory for the caching of configuration data.…”

“…In contrast to the static reconfiguration [9,10], the dynamical reconfiguration is a precondition for the creation of the computing structures, adapted to the requirements of Run Time mode tasks solution [3,[11][12][13]. Firstly, this allows to overcome the limitations of the firm architecture of the high-speed multipurpose computer systems and to approach the real processing performance to the declared …”

The development of means of definition of the optimum ratio of computational algorithm and the reconfigurable structure

“…The most known are resource reuse [1], caching of configuration data [2], forward reconfiguration [4], hardware tools of input/output acceleration [3] and optimization of the virtual structure of configuration data [5]. Each of them is based on the maximum possible reconfiguration acceleration of type "Best Effort" without any optimization of space solution and excluding hardware and technological limitations of the FPGA.…”

“…In recent years, the development of the field-programmable gate arrays (FPGA), which are dynamically reconfigurable, made preconditions and new possibilities for increasing the efficiency of parallel computing systems by making it possible to reconfigure a computing system at run-time [1][2][3]. However, an effective implementation of tasks mapping on the dynamically reconfigurable system is connected with great inefficient wastes of time and performance during its reconfiguration [1,2].…”