The development of means of definition of the optimum ratio of computational algorithm and the reconfigurable structure

Abstract

of the FPGA chips and can be effectively used to solve tasks of big size. Analysis of literature and the given problemsThere are a lot of methods and technologies for reconfiguration overhead reduction. The most known are resource reuse [1], caching of configuration data [2], forward reconfiguration [4], hardware tools of input/output acceleration [3] and optimization of the virtual structure of configuration data [5]. Each of them is based on the maximum possible reconfiguration acceleration of type "Best Effort" without any optimization of space solution and excluding hardware and technological limitations of the FPGA. Overcoming the space limitations of the FPGA is done with standard tools, for example, defragmentation of the computational surface of the FPGA [1, 2], loading out non-critical configuration [1, 2, 4], which brings an additional overhead to the reconfiguration.Granularity is considered as an effective space solution in the field of parallel computation [6]. The reconfiguration possibilities of the computing structure give perspectives to build an ideal computing structure for each task by varying the granularity level. Well-known methods and tools to vary