A WLAN RF CMOS PA with adaptive power cells

Joo, Taehwan; Koo, Bonhoon; Hong, Songcheol

doi:10.1109/rfic.2013.6569600

Cited by 11 publications

(9 citation statements)

References 12 publications

(10 reference statements)

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“…With proposed CG bias circuit, PA shows 1 dB improvement in linear output power at 235 dBc IMD 3 with 2-tone simulation. In measurement, it improves 0.7 dB in linear output power at 228 dB EVM in comparison to previous work [2]. Therefore, it is shown that the CMOS PA is stabilized and linearized with the proposed CG bias network.…”

Section: Design Of Cg Bias Circuit With Reduced Sensitivitymentioning

confidence: 61%

A WLAN CMOS power amplifier with insensitive bias circuits

Joo

Hong

2016

Micro & Optical Tech Letters

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A CMOS power amplifier (PA) for IEEE 802.11b/g/n/ac applications is presented, which is implemented with a 0.13-mm standard RF CMOS process. Integrated bias circuits for the common source (CS) and common gate (CG) power transistors are proposed, which reduce the performance sensitivities of the PA according to the variations of the bias voltage and output power. Measurements show that the proposed power amplifier achieves 17.2 dBm output power with 8.1% PAE at 234 dB EVM with MCS8, 256QAM, 40 MHz, 802.11ac signal source.ABSTRACT: This article proposes a compact wide bandwidth band pass filter (BPF) with a stepped impedance resonator (SIR) and an S-shaped coupled spiral resonator. The SIR has a wide bandwidth while the Sshaped coupled line has a compact structure due to the spiral type resonator. The BPF used the S-shaped folded structure instead of the k g /4 transmission line to reduce the size and to enhance the performance of the BPF. The via-hole was not used in order to keep the design simple. Due to the narrow coupling gap, the bandwidth of conventional BPFs can barely exceed 40%. However, in this work, the proposed BPF achieved a bandwidth of 68%, which is larger than the conventional filter. The experimental results in terms of insertion loss (S 21 ) and return loss (S 11 ) are 0.61 dB and 15.7 dB at 5.3 GHz. The smaller size of the BPF is suitable for microwave communication systems.

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Section: Design Of Cg Bias Circuit With Reduced Sensitivitymentioning

confidence: 61%

A WLAN CMOS power amplifier with insensitive bias circuits

Joo

Hong

2016

Micro & Optical Tech Letters

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“…The proposed quasi-DPA has a folded CT in the output matching network, and this provides several advantages, namely, reduced insertion loss, small size, and wideband characteristics. In addition, the quasi-DPA uses the adaptive power cell (APC) technique, which was already studied regarding the linearity of the main amplifier [14]. An adaptive bias circuit (ADB) [15] was designed for the auxiliary amplifier, and it is biased in class-C.…”

Section: Design Of a Quasi-doherty Pa With An Adaptive Power DIVmentioning

confidence: 99%

A Quasi-Doherty SOI CMOS Power Amplifier With Folded Combining Transformer

Kim

Lee

Hong

2016

IEEE Trans. Microwave Theory Techn.

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A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

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“…The major nonlinear characteristics of CMOS PAs are due to capacitance variations. Therefore, there have been many efforts to reduce the capacitance variations of CMOS power transistors . These can be categorized into two methods.…”

Section: Introductionmentioning

confidence: 99%

“…In the first approach, capacitance variations of NMOS's are compensated by those of PMOS's . In the other approach, the capacitances of CMOS transistors are averaged at various biases .…”

Section: Introductionmentioning

confidence: 99%

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A cascode linear power amplifier with reduced capacitance variation of common gate transistors

Jeong

Kang

Joo

et al. 2016

Micro & Optical Tech Letters

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A common‐gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017

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A WLAN RF CMOS PA with adaptive power cells

Cited by 11 publications

References 12 publications

A WLAN CMOS power amplifier with insensitive bias circuits

A WLAN CMOS power amplifier with insensitive bias circuits

A Quasi-Doherty SOI CMOS Power Amplifier With Folded Combining Transformer

A cascode linear power amplifier with reduced capacitance variation of common gate transistors

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