A CMOS linear PA for IEEE 802.11 b/g applications is implemented in a 0.13 μm process including all matching networks. An adaptive power cell (APC) scheme is proposed to achieve high linear output power and efficiency and applied to the PA, which delivers the output power of 20.5 (19.5) dBm with the PAE of 20.2(17.5)% for an 802.11g modulated signal with the EVMs at -25(-28) dB. Index Terms -AM to AM, AM to PM, CMOS Power Amplifier (PA), adaptive, error vector magnitude (EVM), linearization, IMD3, WLAN, 802.11 b/g
A CMOS power amplifier (PA) for a UHF (860-960 MHz) stationary RFID reader is presented. To design a high power and power efficient CMOS PA, quasi four pair structure and integrated passive device (IPD) transformers are used. An amplitude modulation is performed through the cascode gate with a pulse shaping filter. The chips are fabricated in a 0.18 m CMOS process and IPD. Measurements show output power of 32.8-33.37 dBm and the power added efficiency (PAE) of 51.8-56.1% with the supply voltage 3.0 V. Index Terms-Class-E, CMOS RF power amplifier, integrated passive device (IPD), quasi four pair, stationary RFID reader.
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