CMOS RF Power Amplifier for UHF Stationary RFID Reader

Joo, Taehwan; Lee, Hongtak; Shim, Sunbo; Hong, Songcheol

doi:10.1109/lmwc.2009.2038552

Cited by 17 publications

(6 citation statements)

References 8 publications

(5 reference statements)

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“…Recently, on-chip transformers have become essential in fully-integrated RF CMOS power amplifiers [1][2][3]. In general, this type of transformer serves as an output balun and as a key component of the output matching network in RF CMOS power amplifiers, as shown in Figure 1, assuming that the typical CMOS power amplifier is designed using a differential structure [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

Park¹,

Lee²,

Park³

2019

PIER M

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In this study, we propose a broad-side coupled transformer with reduced capacitance for RF CMOS power amplifier applications. The width of the secondary winding is decreased to reduce parasitic coupling capacitance. Additionally, an auxiliary primary winding is added to improve the coupling between the primary and secondary windings. To prove feasibility of the proposed transformer, we design the transformer using 180-nm RF CMOS technology. From the simulated results of a typical transformer and the proposed broad-side coupled transformer, we successfully find that the parasitic coupling capacitance of the proposed structure is reduced compared to that of a typical structure. Additionally, the auxiliary primary winding increases the maximum available gain of the proposed transformer.

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Section: Introductionmentioning

confidence: 99%

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

Park¹,

Lee²,

Park³

2019

PIER M

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“…Recently, the envelope-tracking (ET) technique has become a popular method to enhance the efficiency of the RF front-end system [1][2][3][4][5][6][7][8][9][10][11][12]. The ET technique can efficiently reduce the power consumption in linear RF power amplifiers, which consume the greatest amount of electric power among the circuits of the RF front-end [13][14][15][16][17][18]. Although there have been various obstacles to complete the ET technique, many meaningful works have been proposed to improve and analyze its feasibility [5][6][7][8][9][10][11][12]19,20].…”

Section: Introductionmentioning

confidence: 99%

Analysis of shoot‐through current of supply modulator for envelope‐tracking techniques

Yoo

Yoon

Lee

et al. 2015

Micro & Optical Tech Letters

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In this work, we analyze the conduction and switching losses of a supply modulator for envelope‐tracking techniques. In particular, the conduction and switching losses in the class‐D chain of the supply modulator are calculated to enhance the efficiency of the supply modulator. From the calculated results, the number of stages and fan‐out in the multiple stages of the class‐D chain are optimized. To verify the feasibility of the analyzed results, we designed a supply modulator using a 180‐nm RF CMOS process. From the measured results, we successfully prove the feasibility of the analyzed results. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1579–1983, 2015

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“…Accordingly, the DAT provides successful solutions for the output matching networks of CMOS power amplifiers. Various studies related to CMOS power amplifiers using a DAT have been reported . Notably, with application of a DAT as the output matching network, the efficiency of the CMOS power amplifier has been dramatically improved.…”

Section: Introductionmentioning

confidence: 99%

Split driver stages for a switching mode power amplifier with multipairs of power stages

Seo

Park

2014

Micro & Optical Tech Letters

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In this study, we analyze the effects of a power splitter on the output power and the power consumption of a CMOS power amplifier using a distributed active transformer as an output balun. On the basis of the analyzed results, we propose a split driver stage structure to mitigate the undesired effects of the conventional power splitter. In the proposed structure, the power splitter is located between the first and second driver stages to isolate the input node of the power stage from the parasitic components of the power splitter. To verify the feasibility of the proposed structure, we designed conventional and proposed 1.9‐GHz CMOS power amplifiers using 0.11‐µm RF CMOS technology. The measured efficiency and output power of the proposed amplifier are improved compared to those of the conventional amplifier. From the measured results, we successfully verify the feasibility of the proposed split driver stage structure. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2341–2345, 2014

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CMOS RF Power Amplifier for UHF Stationary RFID Reader

Cited by 17 publications

References 8 publications

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

Analysis of shoot‐through current of supply modulator for envelope‐tracking techniques

Split driver stages for a switching mode power amplifier with multipairs of power stages

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