A Quasi-Doherty SOI CMOS Power Amplifier With Folded Combining Transformer

Abstract

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

Mid-band 5G wireless network power amplifier research

“…However, a quarter wave TLine is hard to implement in CMOS as the losses would simply be too high (Reynaert, Cao et al, 2016). Several papers (Ryu, Jang et al, 2014;Reynaert, Cao et al, 2016;Kim, Lee & Hong, 2016) report using series combining transformers in order to imitate the loadpull effect. The effect is reduced, comparing to the traditional DPA, but the benefit of combining a Class AB and a Class C PA still results in a higher overall efficiency and a possibly increased bandwidth.…”

“…The effect is reduced, comparing to the traditional DPA, but the benefit of combining a Class AB and a Class C PA still results in a higher overall efficiency and a possibly increased bandwidth. The latter version of DPA is referred to as quasi-DPA (Kim, Lee & Hong, 2016). The same paper reported a quasi-DPA with a 44.4% PAE at P sat = 30.7 dBm and a 39.8% at 3.5 dB back-off.…”

A high power CMOS cascode power amplifier with adaptive dynamic bias control for linearity enhancement

“…However, a single‐ended class‐AB CMOS PA can hardly meet the more and more stringent requirement of linearity and high power capacity for wireless standards, simultaneously. Several linearization techniques—gm linearization technique, digital predistortion (DPD), harmonic termination (HT), interactive AM‐AM modulation, and dynamic gate bias—were proposed to overcome the disadvantages. Because the performance of a class‐AB PA is strongly dependent on its gate bias condition, integrated adaptive dynamic bias (ADB) network can be utilized to set the optimum bias for linearization.…”

Fully-integrated linear CMOS power amplifier with proportional series combining transformer for S-Band applications

“…Doherty power amplification exhibits high efficiency over a wide range of output power, but the =4 transmission lines are usually difficult to be integrated in a single die [9]. Transformer power combining technique can dynamically modulate the load by channel switching, hence it is able to keep the high efficiency at back-off region.…”