A high power CMOS cascode power amplifier with adaptive dynamic bias control for linearity enhancement

Abstract

This work presents both high power and high linearity CMOS cascode power amplifier (PA) with adaptive dynamic bias (ADB) circuit. The ADB circuit sets appropriate gate bias for the common source and common gate (CG) amplifiers according to the input envelope signal, significantly improving the linearity. Meanwhile, harmonic termination circuits are introduced at the gate of the CG amplifier and the center-tap node of the output transformer to short the second harmonic component to ground, further improving the linearity. In addition, this work utilizes an on-chip series-connected transformerbased power combiner to enhance output power. A fully integrated differential PA including the ADB circuit is fabricated in 0.13 μm radio frequency silicon-oninsulator technology. From 2.5 V supply voltage, the proposed PA produces a saturated output power of 30.3 dBm with a peak power-added efficiency of 43.1%. Thanks to the linearization techniques, the proposed PA transmits 23.5 dBm average linear output power with 3% error vector magnitude for a 20-MHz 64-QAM orthogonal frequency division multiplexing modulated signal without any digital predistortion circuits. K E Y W O R D Sadaptive dynamic bias, harmonic termination, linearization, silicon-oninsulator, transformer-based power combiner

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“… Linear PAE across linear output power for the proposed linearity enhancement techniques [ 116 , 118 , 119 , 121 , 123 , 124 , 129 , 132 , 133 , 134 , 135 , 136 , 137 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , 149 , 150 ]. …”

“…This CMOS PA achieved a linear output power of 17.5 dBm at 650 MHz. Furthermore, J. Ren et al (2020) introduced a CMOS PA with an adaptive bias circuit that generated a precise biasing voltage according to the input envelope RF signal [147]. This CMOS PA also employed harmonic termination circuits at the gate of the common-gate PA and the center-tap node of the output transformer.…”

“…Figure 25. Linear PAE across linear output power for the proposed linearity enhancement techniques[116,118,119,121,123,124,129,[132][133][134][135][136][137][142][143][144][145][146][147][148][149][150].…”