A wired-AND transistor: Polarity controllable FET with multiple inputs

Simon, Maik; Trommer, Jens; Liang, B.; Fischer, D.; Baldauf, Tim; Khan, Muhammad Moazzam; Heinzig, André; Knaut, Martin; Georgiev, Yordan M.; Erbe, Artur; Bartha, Johann W.; Mikolaiick, T.; Weber, Walter M.

doi:10.1109/drc.2018.8442159

Cited by 32 publications

(15 citation statements)

References 8 publications

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“…Consequently, the two CGs can be used as input signals enabling a wired-AND gate. [25,29] Figure 4a shows a colored SEM image of the used device architecture with two CGs between the PGs. As for the wired-AND gate the current through the transistor defines the logical output, adapting to conventional CMOS technology, a resistor or even another three top-gate Al-Si NW RFET can be used to convert the current to a logical output at a desired voltage level.…”

Section: Wwwadvelectronicmatdementioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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Section: Wwwadvelectronicmatdementioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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show abstract

“…Thereto, the injection of undesired carriers, i.e., the undesired branch of the ambipolar transfer characteristics, is suppressed by structures with multiple independent gates. Recent attempts include implementations with two 9 , three 22 , or even more frontgates 23 . Also buried gates 24 or a mixture of front and backgates 11,25 have been used.…”

Section: Back-bias Reconfigurable Field Effect Transistormentioning

confidence: 99%

Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor

et al. 2022

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Reconfigurable field effect transistors are an emerging class of electronic devices, which exploit a structure with multiple independent gates to selectively adjust the charge carrier transport. Here, we propose a new device variant, where not only p-type and n-type operation modes, but also an ambipolar mode can be selected solely by adjusting a single program voltage. It is demonstrated how the unique device reconfigurability of the new variant can be exploited for analog circuit design. The non-linearity of the ambipolar mode can be used for frequency doubling without the generation of additional harmonics. Further, phase shifter and follower circuits are enabled by the n- and p-type modes, respectively. All three functions can be combined to create a 3-to-1 reconfigurable analog signal modulation circuit on a single device enabling wireless communication schemes. Both, the concept as well as the application have been experimentally demonstrated on industrial-scale fully-depleted SOI platform. The special transport physics in those structures has been analyzed by TCAD simulations as well as temperature dependent measurements.

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“…However, in order to deal with the charge sharing problem, we will exploit a completely different feature of those devices. It has been shown, both by simulations [21] and measurements [11], [12] that MIGFETs support an internal wired-AND functionality, i.e. a single transistor can be described as an equivalent circuit of several MOSFETs in series.…”

Section: Schottky Barrier Based Transistors With Multiple Indepementioning

confidence: 99%

Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Trommer

Simon

Slesazeck

et al. 2020

IEEE J. Electron Devices Soc.

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Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given circuit and require careful optimization of device sizes. Here we propose a simple CMOS-technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Circuit layouts and design examples are discussed, which elucidate the fundamental differences in circuit topology to classical CMOS designs. For example it is shown that dynamic gates from MIGFET scale much better with stack height of long serial networks, leading to an increased circuit performance, while also providing higher signal stability.

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A wired-AND transistor: Polarity controllable FET with multiple inputs

Cited by 32 publications

References 8 publications

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor

Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

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