Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Trommer, Jens; Simon, Maik; Slesazeck, Stefan; Weber, Walter M.; Mikolajick, Thomas

doi:10.1109/jeds.2020.2986940

Cited by 10 publications

(4 citation statements)

References 28 publications

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“…[26] Additionally, it has been predicted by simulations that exploiting three-gate RFETs, compact realizations of XOR and majority (MAJ) based combinatorial circuits can be envisioned using a lower number of transistors than in classical CMOS technology. [8] Based on these investigations a number of circuit level features, such as dynamic reconfiguration, [26,27] intrinsic XOR, [28] and wired-AND capabilities [29] as well as control of threshold voltage, [30] and suppression of parasitic charge sharing effects in dynamic logic gates, [31,32] have been demonstrated for RFETs, providing additional benefits over their CMOS counterparts. In this respect, fabricating reliable and reproducible metal-semiconductor junctions is essential, as the injection of charge carriers highly depends on the metal-semiconductor interface, junction area, and its incorporated energy barrier.…”

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confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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“…[13] Importantly, the possibility of changing the configuration of each transistor within a circuit enables a reconfiguration of its specific logic functions during operation. [32] Further, the bidirectional nature of reconfigurable transistors is a clear advantage for flexible and adaptive circuit design, as equivalent results can be obtained by swapping the signals between source/drain and V PG /V CG . [9] Considering that, simulations of multi-gate Ge-based RFET devices suggest a possible RFET operation down to a channel length of approximately L Ge = 50 nm, [16] our prototyping platform may paves the way for the development of key components of high-performance and low-power reconfigurable circuits, providing a prototyping platform for future energy-efficient systems as well as hardware security integrated circuits.…”

Section: Resultsmentioning

confidence: 99%

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

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Sistani

Lipovec

et al. 2021

Adv Materials Technologies

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A popular approach to overcome this limitation is the course-grain reconfiguration, i.e. the signal routing to predefined logic blocks as practiced in field programmable gate arrays (FPGA). [1] This approach nevertheless leads to a high latency in data transfer and substantial chip area consumption since few active regions are not utilized at once. Distinctly, the ansatz of reconfiguration of elementary function blocks, i.e. the fine-grain reconfiguration, gives rise to a paradigm change where devices and circuits are actively redesigned after manufacturing and noteworthy even at runtime. Thereto, combinational circuits have shown benefits in area and power consumption by reconfiguration of complete logic blocks. [2] The building blocks for such circuits are RFETs, capable of merging the electrical properties of unipolar p-and n-type FETs into a single type of device with identical technology, geometry and composition. [3][4][5] Notably, RFETs do not require doping in contrast to classical FETs. Thereto, a device layout with independent gates is used to induce an additional energy barrier to the channel that blocks the undesired charge carrier type and therefore favors p-or n-type operation respectively. Consequently, reducing the technological fabrication complexity, they enable dynamic programming of circuits at the device level. [3,5] Prominent applications of such RFET devices are currently arising in the area of hardware security [6] and in highly integrated combinational and sequential logic. [5,7] Different channel materials have been employed to realize RFETs. With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes. In this sense, Ge and SiGe have been identified as promising channel materials due to their reduced bandgap compared to the one of Si. Since the highest fraction of transport relevant for device and circuit performance is dictated by quantum mechanical tunneling of charge carriers [12] the use of Ge and Si x Ge 1-x channels Conventional field-effect transistor (FET) concepts are limited to static electrical functions and demand extraordinarily steep and reproducible doping concentration gradients. Reaching the physical limits of scaling, doping-free reconfigurable field-effect transistors (RFETs) capable of dynamically altering the device operation between p-or n-type, even during runtime, are emerging device concepts. In this respect, Ge has been identified as a promising channel material to enable reduction of power consumption and switching delay of RFETs. Nevertheless, its us...

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“…Reconfigurable devices are promising for applications in hardware security, where they can be applied to camouflage the circuit functionality [15], [16]. Furthermore, recent studies have shown that reconfigurable transistors, in particular devices with multiple independent gates, improve signal integrity in dynamic logic gates [17], [18]. They also have potential to foster non-traditional digital design styles, such as asynchronous and reversible logic [19].…”

Section: Related Workmentioning

confidence: 99%

Quantitative Characterization of Reconfigurable Transistor Logic Gates

et al. 2020

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We present a new approach for early analysis of logic gates that is based on formal methods. As device technology research takes years and is very expensive, it is desirable to evaluate a technology's potential as early as possible, which is hard to do with current techniques. The actual impact of new devices on circuit design and their performance in complex circuits, are difficult to predict using simulationbased techniques. We propose a new approach that supplements simulation-based analysis and enables the development of standard cells alongside ongoing fundamental device research. Thereby, it potentially shortens the development cycle and time to market of a new technology. We develop a new discrete charge-transport model for electrical networks and a new flexible model of polarity-reconfigurable transistors as our formal basis. These models make circuit designs accessible to an analysis using probabilistic model checking and power our experiments. Besides worst-case analysis, we leverage measures hardly accessible to simulation such as average delay and average energy consumption per switching operation. We complement this with an automated design-space exploration that yields all reasonable implementations of a switching function built with reconfigurable transistors. After demonstrating the accuracy of our approach by comparison with finite element method analysis results, we undergo a comprehensive design-space exploration and analysis of the 3-minority function. The quantitative results are ranked with respect to various performance metrics, and we analyze the most promising circuit implementations in detail to derive a design guide that yields the best implementation for given statistics of the input patterns.

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Inherent Charge-Sharing-Free Dynamic Logic Gates Employing Transistors With Multiple Independent Inputs

Cited by 10 publications

References 28 publications

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

Quantitative Characterization of Reconfigurable Transistor Logic Gates

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