A wafer-scale 3-D circuit integration technology

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

“…In addition, traditional objectives, such as wire length and area, are insufficient for 3-D circuits, particularly [28], [47] and (b) 3-D SOI processes [9].…”

“…The majority of manufacturing technologies for threedimensional (3-D) integration include die or wafer bonding, resulting in dense polylithic systems where standard field-effect transistors are utilized to implement logic functions [1]- [9]. Consequently, the intrinsic speed of a logic gate in 3-D circuits remains constant, while the interconnect performance can be significantly improved by vertically stacking the connected planes as compared to traditional two-dimensional (2-D) circuits.…”

“…Both capacitive and inductive communication techniques have been developed for contactless 3-D circuits [37]- [39]. Although these techniques reduce or eliminate the need for galvanic connections among the planes of a 3-D circuit, issues such as dc power supply, interference from adjacent signals, and the physical area of (a) System-in-package [32] and (b) a 3-D circuit with dense through silicon vias [8], [9]. Two different bonding styles, front-to-front and back-to-front, are illustrated.…”

High-κ Al2O3 material in low temperature wafer-level bonding for 3D integration application

“…7 A great number of materials have been applied to achieve wafer-level bonding for 3D integration circuit (IC) applications; the most popular include polymer adhesive materials, 8,9 intermetallic compounds, 10,11 diffusion metal materials (such as gold, 12 aluminum, 13 and copper,) 14 and silicon oxide. 15 Amongst these different materials, copper and oxide are most attractive as they are widely used as the interconnectors and interlayer dielectrics based on CMOS backend processing. 3 Some studies have indicated that Cu-to-Cu wafer-level thermo-compression bonding is typically performed at 350-400 • C. 14,16,17 With developments in surface treatments, especially the application of prebonding passivation based on a self-assembled monolayer (SAM), 18 high bonding quality can be obtained at an adequately low temperature (typically 300 • C or below).…”

Two Transistor Current Mode Active Pixel Sensor

“…Other techniques for high resolution imaging have included capacitor and/or BJTs within each pixel in order to control the pixel output or reset phase of the photo diode [3], [4]. A small pitch, high fill factor image sensor was fabricated in a stack 3-D technology, where the photodiode was placed in a top tier and read out circuitry was placed in subsequent tiers [5]. The novel stack 3-D fabrication technology has created new possibilities for high resolution image sensors.…”