A VLSI design of a pipeline Reed-Solomon decoder

Abstract

A pipeline structure of a trsnsform decoder similsr to s systolic array is developed to decode Reed-Solomon (ES) codes. The error locator polynomial is computed by a modified Euclid's algorithm which svoids computing inverse field elements. The new decoder is regular sod simple, snd nsturslly suitsble for VLSI implementation.

Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems

“…The TME algorithm produces a zero coefficient at the x 2t term of Ω (c) (x) by performing (8) and (9) in each iteration. Together with the control mechanism of u 0 and 2l ≤ k in (10), the TME algorithm removes the need for the degree computation and comparison in conventional ME algorithms [1]. After 2t iterations, the desired Ω (b) (x) and Λ (b) (x) are obtained simultaneously, and the results can be directly used in the Chien search and the Forney algorithm for finding the error locators and the error values [2].…”

“…+ αx + α 2 is produced by performing (8), (9), and (11) in the k-th iteration, the degree of Ω is regarded as 15 for the next iteration. Let the notations Ω(x) and Λ(x) denote the error evaluator and error locator polynomials in the conventional ME algorithm [1], respectively, and deg(F(x)) represent the degree of F(x). Note that Ω(x) and Λ(x), respectively, can be used instead of Ω(x) and Λ(x) defined in (4) to obtain the error locations and the corresponding error values when performing the Chien search and the Forney algorithm.…”

“…Two main decoding algorithms are commonly adopted to solve the key equation: the modified Euclidean (ME) algorithms [1]- [7] and the Berlekamp-Massey (BM) algorithms [8]- [13]. Conventionally, architectures based on the BM algorithm for solving the key equation have the advantage of low computational complexity.…”

Two-parallel Reed-Solomon based FEC architecture for optical communications

“…Currently, the RS(255, 239) code is commonly used in high-speed (40-Gb/s and beyond) fiber optic systems. However, as the data rates approach 40-Gb/s and beyond, all existing RS decoders using a systolic-array structure [2,3,4] cause relatively huge hardware complexity and power consumption, which cause difficulties in system-level integration.…”

“…and wireless systems, as well as in networking communications [1,2,3,4,5]. Due to increasing demand for high capacity of optical communications, the high-speed low-power implementations of RS decoders are desirable to meet higher data rate for system-level integration.…”