A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance

Asra, Ram; Shrivastava, Mayank; Murali, K. V. R. M.; Pandey, Raju; Gossner, Harald; Rao, V. Ramgopal

doi:10.1109/ted.2011.2140322

Cited by 142 publications

(44 citation statements)

References 22 publications

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“…Asra et al has presented a new structure for tunnel FET in [2]. The device shows better static and dynamic per formances for sub-1-V operations.…”

Section: Prev Ious Workmentioning

confidence: 99%

“…Such a reduced swing is a necessary requirement for the ultra-low power and ultra-low voltage operation for the next genera tion of transistors [2], [3], [4]. Although there are other possibilities also like Carbon Nano Tube (CNT), the nano-electromechanical (NEM)-based devices, super steep sub-threshold-slope complementary MOSFETs and other impact ionization-based devices.…”

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confidence: 99%

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A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET

Menka

Bulusu

Dasgupta

2012

2012 Annual IEEE India Conference (INDICON)

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In this p a p er a TCAD method to determine surface electron density of a three terminal (3T) symmetric double gate silicon n-tunnel FET (DG Si nTFET) is p resented. This research p a p er p resents the changes in the channel surface electron density of symmetric n-Tunnel Field Effect Transistor (nTFET) devices. The p hysical reasoning behind the modeling a pp roach has also been p resented. It has been observed that the electron density in n-TFET, goes much beyond the do p ing concentration in channel. Also, unlike MOSFET, the electron density in sub threshold regime de p ends on the drain voltage. For lower drain voltages «O.4V) the electron density is much higher than the do p ing concentration in channel, but for higher drain voltages, electron density below threshold might be much lesser than the channel do p ing concentration.

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“…Asra et al has presented a new structure for tunnel FET in [2]. The device shows better static and dynamic per formances for sub-1-V operations.…”

Section: Prev Ious Workmentioning

confidence: 99%

mentioning

confidence: 99%

A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET

Menka

Bulusu

Dasgupta

2012

2012 Annual IEEE India Conference (INDICON)

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“…Moreover the subthreshold swing of the MOS is limited to 60mV/decade at room temperature [3]. To overcome this, several alternative device structures such as tunnel field-effect transistors (TFETs) [4], impact ionization Metal oxide semiconductor field effect transistors (MOSFETs) [5], MOSFETs with a ferroelectric insulator as a gate oxide [6] and sandwich tunnel barrier FETs [7] have been proposed. TFET is a promising device to replace the conventional MOSFET for low power applications [8].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

Samuel¹,

Balamurugan²

2014

Journal of Electrical Engineering and Technology

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-In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

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“…In the past few years, several research groups have indicated that, I OFF of TFET will be limited by gate leakage current. Still its effect has been neglected in reported research findings [14][15][16]. Neglecting gate leakage leads to underestimation of sub threshold slope, I OFF and exceedingly high values of I ON /I OFF , particularly when high-k dielectrics are not used.…”

Section: Introductionmentioning

confidence: 99%

Effect of gate dielectric thickness on gate leakage in tunnel field effect transistor

Chaturvedi

Goyal

2012

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

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Gate leakage is one of the important parameter expected to limit the performance of Tunnel FETs. We have simulated the effect of gate dielectric thickness on gate leakage in Tunnel FETs, using two dimensional numerical simulations. It has been observed that gate leakage considerably affects the subthreshold characteristics of TFETs. It was found to be most important component of off-state current and should be considered in future TFET device design. Effects of gate metal workfunction on device characteristics, particularly, gate leakage and origin of reverse tunneling at drain have also been discussed.

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A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance

Cited by 142 publications

References 22 publications

A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET

A TCAD approach to evaluate channel electron density of double gate symmetric n-tunnel FET

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

Effect of gate dielectric thickness on gate leakage in tunnel field effect transistor

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