A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips

Lee, Matthew Kay Fei; Cui, Yingnan; Somu, Thannirmalai; Luo, Tao; Zhou, Jun; Tang, Wai Teng; Wong, Weng-Fai; Goh, Rick Siow Mong

doi:10.1145/3291054

Cited by 38 publications

(22 citation statements)

References 47 publications

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“…However, it only implements the simulation function. A system-level simulator [11] for ReRAM-based neuromorphic computing chips integrated Network-on-Chip (NoC) and ReRAM and focused on the simulation of Spiking Neural Network (SNN), not DNN. Moreover, this work did not involve any training algorithm or network mapping.…”

Section: Related Workmentioning

confidence: 99%

“…We propose such an open source framework called XB-SIM . Compared with existing studies on software tools that allow the modeling of ReRAM devices [8] or the simulation of synaptic devices, crossbars [9] , and even accelerator architectures [10,11] , our work is the only one that supports the complete end-to-end codesign process of RNA, which involves training a real Deep Neural Network (DNN), deploying NN parameters onto hardware efficiently (also called mapping), and simulation.…”

Section: Introductionmentioning

confidence: 99%

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XB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design

Fei

Zhang

Zheng

2021

Tinshhua Sci. Technol.

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Resistive Random Access Memory (ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance. However, design of these accelerators faces a number of challenges including imperfections of the ReRAM device and a large amount of calculations required to accurately simulate the former. We present XB-SIM , a simulation framework for ReRAM-crossbar-based Convolutional Neural Network (CNN) accelerators. XB-SIM can be flexibly configured to simulate the accelerator's structure and clock-driven behaviors at the architecture level. This framework also includes an ReRAM-aware Neural Network (NN) training algorithm and a CNN-oriented mapper to train an NN and map it onto the simulated design efficiently. Behavior of the simulator has been verified by the corresponding circuit simulation of a real chip. Furthermore, a batch processing mode of the massive calculations that are required to mimic the behavior of ReRAM-crossbar circuits is proposed to fully apply the computational concurrency of the mapping strategy. On CPU/GPGPU, this batch processing mode can improve the simulation speed by up to 5.02 or 34.29. Within this framework, comprehensive architectural exploration and end-to-end evaluation have been achieved, which provide some insights for systemic optimization.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

XB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design

Fei

Zhang

Zheng

2021

Tinshhua Sci. Technol.

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“…To speed up the study on non-ideal effects on memristor crossbar of MBNNs, the simulation is futher carried out by a chip-like framework implemented in C++ software [18]. In this case, we considered various non-ideal effects such as yield rate of memristor array, memristor conductance fluctuation, and reading noise in memristor crossbar to evaluate the robustness of the proposed method.…”

Section: Non-ideal Effects On Memristor Crossbarmentioning

confidence: 99%

“…However, that is not the entire beauty of it. Non-linearity, inconsistent periodicity, and asymmetry in the memristor's conductance modulation, drift and failure in read/write operation, and other non-ideal factors could cause tremendous difficulties when the memristor is introduced in pattern recognition and other similar AI applications [16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Zhao

Wang

et al. 2021

Electronics

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Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

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“…[11]. Our framework can be used to evaluate other SNN mapping strategies, including those that target mapping SNNs to a single crossbar [14].…”

Section: Conclusion and Future Outlookmentioning

confidence: 99%

A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing

Balaji

Song

Das

et al. 2019

IEEE Comput. Arch. Lett.

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Neuromorphic architectures with non-volatile memory (NVM) implement biological neurons and synapses to execute spiking neural networks (SNNs). To access synaptic weights, an NVM cell's peripheral circuit drives current through the cell using a high bias voltage, generated from an on-chip charge pump. High-voltage operations induce aging of CMOS devices in the charge pump, leading to negative bias temperature instability (NBTI) and hot carrier injection (HCI) generated defects. Therefore, charge-pump aging poses a significant threat to the operating lifetime of neuromorphic architectures. Discharging a stressed charge pump periodically can lower its aging rate, but makes the architecture unavailable to process spikes while its charge pumps are being discharged. This introduces delay in spike propagation, which impacts inter-spike interval (ISI), leading to information loss and challenging the integrity of SNNs. This performance and lifetime trade-off depends on the SNN workload being executed. In this paper, we propose a novel framework to exploit workload-specific performance and lifetime trade-offs in neuromorphic computing. Our framework first extracts the precise times at which spikes are generated on all synapses of a SNN workload. This timing information is then used wihtin a new analytical formulation to estimate aging of charge pumps based on the SNN's mapping to the hardware and the power delivery architecture of charge pumps. We use the developed framework to optimize the mapping of neurons and synapses at design time and to schedule the discharge of stressed charge pumps at run time to maximize their lifetime, without significantly hurting the workload's performance.

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A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips

Cited by 38 publications

References 47 publications

XB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design

XB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design

A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing

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