A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing

Balaji, Adarsha; Song, Shihao; Das, Anup; Dutt, Nikil; Krichmar, Jeff; Kandasamy, Nagarajan; Catthoor, Francky

doi:10.1109/lca.2019.2951507

Cited by 36 publications

(29 citation statements)

References 18 publications

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“…DecomposeSNN [16] decomposes an SNN to improve the cluster utilization. There are also performance-oriented SNN mapping approaches such as [7,11,15,86], energy-aware SNN mapping approaches such as [101], circuit aging-aware SNN mapping approaches such as [10,67,84,88,91], endurance-aware SNN mapping approaches such as [93,99,102], and thermal-aware SNN mapping approaches such as [100]. These approaches are evaluated with emerging SNN based applications [9,31,43,50,64,75], which we also use to evaluate DFSynthesizer.…”

Section: Related Workmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song

Chong

Balaji

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches.

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Section: Related Workmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song

Chong

Balaji

et al. 2022

ACM Trans. Embed. Comput. Syst.

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show abstract

Section: Related Workmentioning

confidence: 99%

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Song¹,

Chong²,

Balaji³

et al. 2021

Preprint

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tilebased neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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“…Figure 1 illustrates the three design methodologies supported by NeuroXplorer -1) platform-based design, 2) hardware-software co-design, and 3) design-technology co-optimization. We have used NeuroXplorer to optimize for system-level design metrics, including energy [9,19,67], latency [3,17], throughput [59], resource utilization [2,11], circuit aging [5,37,57,61], and endurance [65,66,68].…”

Section: Neuroxplorer: High-level Designmentioning

confidence: 99%

“…Therefore, in addition to cluster placement when admitting a machine learning model to hardware, NeuroXplorer also supports monitoring key performance statistics collected from the hardware during model execution. Such statistics can uncover bottlenecks, allowing improving system-level metrics such as energy [10] and circuit aging [5,64] through remapping of the neurons and synapses to the hardware.…”

Section: Runtime Managermentioning

confidence: 99%

“…NeuroXplorer's hardware simulator can perform exploration with transistor technologies such as CMOS and FinFET that are used for the neurons and the peripheral circuitry in each tile, and Non-Volatile Memory (NVM) technologies such as Phase-Change Memory (PCM) [13], Oxide-Based Resistive Random Access Memory (OxRRAM) [41], Ferroelectric RAM (FeRAM) [47], and Spin-Transfer Torque Magnetic or Spin-Orbit-Torque RAM (STT/ SoT-MRAM) [70] used for synaptic weight storage. 5 We now describe the simulator. Figure 11 shows the capabilities of the hardware simulator of NeuroXplorer.…”

Section: Detailed Design Of Neuromorphic Hardware Simulatormentioning

confidence: 99%

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NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks

Balaji¹,

Song²,

Titirsha³

et al. 2021

Preprint

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Recently, both industry and academia have proposed many different neuromorphic architectures to execute applications that are designed with Spiking Neural Network (SNN). Consequently, there is a growing need for an extensible simulation framework that can perform architectural explorations with SNNs, including both platform-based design of today's hardware, and hardwaresoftware co-design and design-technology co-optimization of the future. We present NeuroXplorer, a fast and extensible framework that is based on a generalized template for modeling a neuromorphic architecture that can be infused with the specific details of a given hardware and/or technology. NeuroXplorer can perform both low-level cycle-accurate architectural simulations and high-level analysis with data-flow abstractions. NeuroXplorer's optimization engine can incorporate hardware-oriented metrics such as energy, throughput, and latency, as well as SNN-oriented metrics such as inter-spike interval distortion and spike disorder, which directly impact SNN performance. We demonstrate the architectural exploration capabilities of NeuroXplorer through case studies with many state-of-the-art machine learning models. CCS CONCEPTS• Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies.

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A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing

Cited by 36 publications

References 18 publications

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks

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