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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches.

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tilebased neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine-learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine-learning programs. Our results demonstrate that DFSynthesizer provides much tighter performance guarantee compared to current mapping approaches. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

The data provided in the article contains bacterial community profiles present on the surface of red algae ( Kappaphycus alvarezii ) isolated directly after collection and after 30 days of cultivation in a closed circulation system. The explants of Kappaphycus alvarezii were cultivated in a laboratory setting under controlled growth conditions for 30 days in order to determine bacteria that could adapt to controlled culture conditions. Amplification and sequencing of bacterial 16S rDNA amplicon were performed on bacterial isolates associated with the seedlings. The 16S rDNA gene sequences were analyzed, trimmed, and assembled into contigs using DNA Baser Sequence Assembler (V5) software. Taxonomic identification for the assembled sequences was achieved using the online BLAST (blastn) algorithm, and the construction of a phylogenetic tree was performed using the MEGA7 software. The data reveals a distinct set of microbial variations between day one and day 30. The phylogenetic tree depicts four major clusters, Vibrio, Pseudoalteromonas, Alteromonas , and Bacterioplanes resident on the surface of the K. alvarezii . Comparison between these two bacterial groups provides evidence of the persistent marine bacteria that adapt to the long-term culture in closed circulation systems. Raw data files are available at the GenBank, NCBI database under the accession number of MZ570560 to MZ570580.

Electrochemical faradic deionization (EDI), one of the most promising research branches of capacitive deionization (CDI), has demonstrated considerable potential for water desalination and ion removal (particularly at medium to low salinity). However, the associated relatively slow anion-capturing kinetics have limited the practical applications of EDI. Based on several studies, researchers have attributed this slow anion-capturing rate to the sluggish conversion-reaction-induced anion-capturing process (as most anion-capturing electrodes belong to the conversion type). Herein, we report a strategy for accelerating the anion-capturing process to enhance the desalination rate of EDI by utilizing an intercalation-type FeOOH electrode. The chloride-driven EDI system equipped with hollandite-type FeOOH nanospindles is found to present a high desalination rate (up to 4.44 mg g−1 min−1) and desalination capacity (51.77 mg g−1). The current study can inspire the future design of ultrafast EDI systems and bring the EDI technique closer to its practical application.

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