A Highly Robust Binary Neural Network Inference Accelerator Based on Binary Memristors

Abstract

Since memristor was found, it has shown great application potential in neuromorphic computing. Currently, most neural networks based on memristors deploy the special analog characteristics of memristor. However, owing to the limitation of manufacturing process, non-ideal characteristics such as non-linearity, asymmetry, and inconsistent device periodicity appear frequently and definitely, therefore, it is a challenge to employ memristor in a massive way. On the contrary, a binary neural network (BNN) requires its weights to be either +1 or −1, which can be mapped by digital memristors with high technical maturity. Upon this, a highly robust BNN inference accelerator with binary sigmoid activation function is proposed. In the accelerator, the inputs of each network layer are either +1 or 0, which can facilitate feature encoding and reduce the peripheral circuit complexity of memristor hardware. The proposed two-column reference memristor structure together with current controlled voltage source (CCVS) circuit not only solves the problem of mapping positive and negative weights on memristor array, but also eliminates the sneak current effect under the minimum conductance status. Being compared to the traditional differential pair structure of BNN, the proposed two-column reference scheme can reduce both the number of memristors and the latency to refresh the memristor array by nearly 50%. The influence of non-ideal factors of memristor array such as memristor array yield, memristor conductance fluctuation, and reading noise on the accuracy of BNN is investigated in detail based on a newly memristor circuit model with non-ideal characteristics. The experimental results demonstrate that when the array yield α ≥ 5%, or the reading noise σ ≤ 0.25, a recognition accuracy greater than 97% on the MNIST data set is achieved.

Binarized neural network of diode array with high concordance to vector–matrix multiplication

“…We demonstrated the BNN operation of an array composed of p + -n-p-n + diodes with bistable characteristics. The component diode exhibited inherent unipolar switching characteristics, and the array was immune to sneak path problems, unlike previously proposed BNNs 11 – 13 , 16 , 43 . In addition to the outstanding bistable characteristics with a high current ratio (approximately 10 8 ), the rectifying characteristics can simplify peripheral neuron circuits.…”

“…Furthermore, it is still difficult for emerging synaptic devices to fully implement analog neural networks (analog input and analog weight) with nonlinear conductance changes and device variations 1 – 4 , 11 – 13 . However, digital synaptic devices are suitable for implementing BNNs because of their binarized weights 13 – 16 .…”

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

“…In this work, the accelerator computing 6-bit computations gives the best results with TLCs as compared to any other configuration. Hence, for a k-bit precision, a bit cell with half-the precision is best suitable for improving the overall accelerator performance with the above-mentioned configuration [30]. However, the results may vary with other network architectures and applications.…”

A Systematic Literature Review on Binary Neural Networks

“…This design supports biterrors reduction. In [152], the authors presented a BNN accelerator with a two-column reference memristor structure to map +1 and -1 weights on the memristor array and remove the sneak current effect. While Y. Qin et al [144] used a W/AlOx/Al2O3/Pt memristor with a column architecture.…”