A Study on the Behavior of Gate Recess Etch by Photoresist Openings on Ohmic Electrode in InAlAs/InGaAs mHEMT Devices

Abstract

In the fabrication of InAlAs/InGaAs metamorphic high-electron-mobility transistor (mHEMT), the determination of whether etching has been completed to the desired gate recess depth is made by measuring whether the drain current through the channel layer has reached the target current. Non-uniformity of the etching rate occurs during wet etching with citric acid. In this study, the cause of that non-uniformity was investigated. We confirmed that an electrochemical potential caused by the electrolyte of the etching solution was induced between the ohmic electrode and the epitaxial layer of the recess region, resulting in a non-uniform etching rate. In particular, the case where the Au of an ohmic electrode is exposed by the monitor window for the measuring channel current was considered. The gate recess etch rate was changed by the presence, location and size of the photoresist openings on the ohmic electrodes.

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

“…In the case of Pt, typical chemical etching characteristics are shown. As in this study, when Au is exposed by the recess monitor opening, it can be predicted that chemical and electrochemical etching properties coexist with reference to the aforementioned report [12].…”

“…In our previous paper, we discussed that the size of the recess monitor opening affects the etching rate [12]. At this time, we intend to discuss the relationship between the etch depth and the line width changed by electron‐beam lithography conditions for a two‐finger gate unit device with the same recess monitor opening size.…”

“…The wafer on which the gate electrode process was completed was passivated by depositing a 50 nm thick SiN film by plasma enhanced chemical vapor deposition. Subsequently, processes, such as via etching of the passivation film, secondary metal deposition for metal–insulator–metal capacitors, and air‐bridge metal formation, were performed to complete the front‐side process for MMIC fabrication [12]. Figure 5 is a SEM image of a unit device with a two‐finger gate with a gate width of 50 μm.…”

“…In the manufacture of compound semiconductor devices, Au is generally used as the uppermost metal electrode layer. We have reported how the size of the monitor opening and the exposed Au area affects gate recess etch characteristics [12].…”

Optimized recess etching criteria for T‐gate fabrication achieving ft = 290 GHz at Lg = 124 nm in metamorphic high electron mobility transistor with In0.7Ga0.3As channel

“…It can be done by developing additional recess pads on source and drain metals, which are coated by e-beam resists. In our previous works, we dealt with the uneven recess etch rate between fingers in multi-finger mHEMT [7] and the etching depth variation according to the foot width of the T-gate [8]. In this paper, we present criteria of performing citric acid-based electrochemical recess etching before T-gate metal evaporation to fabricate high-performance InGaAs HEMTs.…”