A Soft Error Rate Model for MOS Dynamic RAM's

Toyabe, T.; Shinoda, Takashi; Aoki, Masakazu; Kawamoto, H.; Mitsusada, K.; Masuhara, T.; Asai, S.

doi:10.1109/jssc.1982.1051742

Cited by 19 publications

(5 citation statements)

References 6 publications

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“…When the bit lines are in a floating voltage state (e.g., during a read cycle), DRAMs are sensitive to the collection of charge into diffusion regions that are electrically connected to the bit access lines [70]. This collection could arise from any of the access-transistor drains along the bit-line length or from a direct strike to the differential sense amplifier [71]. The bit-line SEU mechanism is the reduction of the sensing signal due to a charge imbalance introduced on the precharged bit lines, either prior to or during the sensing operation.…”

Section: A Seu Mechanisms In Dramsmentioning

confidence: 99%

“…Because the duty cycle of these stages to the overall cycle time increases with increasing overall clock frequency, the bit-line soft error rate is inversely proportional to DRAM cycle time [71]. In contrast, cell upsets are independent of the DRAM cycle time.…”

Section: A Seu Mechanisms In Dramsmentioning

confidence: 99%

“…In contrast, cell upsets are independent of the DRAM cycle time. Bit-line errors also show a strong inverse correlation with the signal charge [71]. As chip densities and speeds grow, bit-line errors are expected to be increasingly important.…”

Section: A Seu Mechanisms In Dramsmentioning

confidence: 99%

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Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

896

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: A Seu Mechanisms In Dramsmentioning

confidence: 99%

Section: A Seu Mechanisms In Dramsmentioning

confidence: 99%

See 1 more Smart Citation

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

896

427

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“…This could better be achieved by introducing a second absorbing surface at the location of the well junction, leading to an infinite sum of terms such as equation 3. 6 Owing to the increase in program run time such a model has not been used in this work.…”

Section: ; M3mentioning

confidence: 99%

Calculation of the soft error rate of submicron CMOS logic circuits

Juhnke

Klär

1995

IEEE J. Solid-State Circuits

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As a prerequisite for predicting the soft-error rate (SER) of CMOS circuits with dynamic registers a method to calculate the SER is presented which takes into account charge collection by drift and diffusion. It has been found that besides collection due to drift, the noise charge collected by diffusion has to be considered to accurately predict the SER of dynamic CMOS circuits. Calculated results are compared to device simulations and SER measurements.

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“…TFs have traditionally been a problem for high density memories, because of the cell small size [12]. Error detecting/correcting codes are widely used to protect them against this kind of errors [13].…”

Section: Introductionmentioning

confidence: 99%

Multiple transient faults in logic: an issue for next generation ICs?

Rossi

Omaña

Toma

et al.

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

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In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations we will show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for Very Deep Submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

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A Soft Error Rate Model for MOS Dynamic RAM's

Cited by 19 publications

References 6 publications

Basic mechanisms and modeling of single-event upset in digital microelectronics

Basic mechanisms and modeling of single-event upset in digital microelectronics

Calculation of the soft error rate of submicron CMOS logic circuits

Multiple transient faults in logic: an issue for next generation ICs?

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