Multiple transient faults in logic: an issue for next generation ICs?

Abstract

In this paper, we first evaluate whether or not a multiple Transient Fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations we will show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for Very Deep Submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

High-Performance Robust Latches

“…For each latch, the table reports the number of susceptible nodes and their kind, the total susceptible area normalized to the total area of the latches, considering only nodes of kind ii) and iii), and the minimum and maximum values of the critical charge obtained considering all susceptible nodes. Finally, the last two columns report the values of the estimated RHiPeR and RHiPeR-CG, as defined in (3) and (4), respectively, whose values have been computed deriving the value of the parameter  from [29] ( = 72  10 12 1/C for the considered 90nm CMOS technology).…”

“…Error correcting codes (ECCs), in particular single error correcting/double error detecting codes, have been successfully employed to guarantee a satisfactory level of memory reliability. Recently, because of the increasing probability of having multiple bit upsets [12], memory designers are facing new and challenging problems.…”

Neutron induced single event multiple transients with voltage scaling and body biasing

“…Along with the scaling of semiconductor devices, single event multiple faults, which is a kind of soft error that two or more nodes are affected by one radiation particle, is becoming a serious problem [1], [2], [3], [4], [5]. Single event multiple faults is mainly classified into single event multiple(-bit) upsets (SEMU), which causes bit flips in two or more memory elements, and single event multiple transients (SEMT), which induces pulses in two or more combinational logic nodes.…”

“…However, no SEMT measurement results have been reported though a few evaluations based on device and circuit simulation are reported [4], [5].…”

VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

“…It is commonly agreed that technology nodes smaller than 65 nm tend to become increasingly vulnerable to single-event upsets, due to their small critical charges and the low voltage swing [3][4][5]. As a consequence the need for fault tolerance emerges, even for non-safety-critical applications.…”