Neutron induced single event multiple transients with voltage scaling and body biasing

Radiation-induced single event upsets (SEUs), or soft errors, have become a dominant factor in the reliability degradation of nanoscale memories. In this paper, based on the SEU physics mechanism, and reasonable layout-topology, a novel soft error hardened memory cell is proposed in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design comparisons for several hardened memory cells in terms of access time (read access time and write access time), power consumption, and layout area are also executed. The main advantage of the proposed cell is that it can provide 100% fault tolerance, which is very useful for memory applications in severe radiation environments. Furthermore, Monte Carlo simulations are carried out to evaluate the effects of process, voltage, and temperature (PVT) variations. From simulations, we confirmed that the proposed cell has exhibited a sufficient multiple-node upset tolerance capability even under PVT variations.

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“…3. Note that in a CMOS 65 nm process the effective range of charge sharing is less than 1.5 between transistors [20]. From Fig.…”

Section: B Seu Recovery Analysismentioning

confidence: 96%

“…However, the scaling down of CMOS technology has resulted in a dramatic increase in the possibility of multiple-node upset [20], [21], so from a critical application designer point of view, the proposed RHM cell is a good choice for providing perfect protection against SEU in memories.…”

Section: B Comparisons Of Cell Area Power and Access Timementioning

confidence: 99%

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

et al. 2015

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“…In low-frequency applications, the SET in data input is hardly to be captured by the clock signal. However, charge sharing [3,15] can lead to single event multiple transient (SEMT) [7,16] in nanometer CMOS technology. As shown in Figure 2, if a SET is generated in flip-flop data input nodes with a SET generated in the clock signal simultaneously, the SET in flip-flop data input may be latched into flip-flop by the SET in flip-flop clock signal.…”

Section: Sedt-induced Seu Mechanismmentioning

confidence: 99%

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Huang

Chen

2016

Sci. China Inf. Sci.

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Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.Keywords single event upset (SEU), single event double transient (SEDT), SEDT-induced SEU, parasitic bipolar effect (PBE), charge sharing CitationHuang P C, Chen S M, Chen J J. Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology. Sci China Inf Sci,

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“…If this charge is accumulated in sensitive regions, it may cause single-event effects (SEE): single-event upsets (SEU) in memory, or single-event transients (SET) in combinational logic. With the [Harada et al 2011]. Transients can be induced even with a separation of 1.5 microns between nodes in this technology.…”

Section: Introductionmentioning

confidence: 99%

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

Kiddie

Robinson

Limbrick

2015

ACM Trans. Des. Autom. Electron. Syst.

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As fabrication technology scales towards smaller transistor sizes and lower critical charge, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs), and with higher operating frequencies, this risk increasingly impacts design logic over memory as well. In order to increase future system reliability, circuit designers need greater awareness of multiple-transient charge-sharing effects during the early stages of their design flow with standard cell placement and routing. To measure the propagation and observability of multiple transients from single radiation events, this work uses several intra-pipeline combinational logic circuits at the 32nm technology node, investigates several different standard cell placements of each design, and analyzes those placements with a novel, physically realistic transient injection and simulation method. It is shown that (1) this simulation methodology, informed by experimental data, provides an increased realism over other works in traditional fault injection fields, (2) different placements of the same circuit where standard cells are grouped by logical hierarchy can result in different reliability behavior and benefits especially useful within the area of approximate computing, and (3) improved reliability through charge-sharing transient mitigation can be gained with no area penalty and minimal speed and power penalties by adjusting the placement of standard cells. ACM Reference Format: Bradley T. Kiddie, William H. Robinson, and Daniel B. Limbrick. 2015. Single-event multiple-transient characterization and mitigation via alternative standard cell placement methods.

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Neutron induced single event multiple transients with voltage scaling and body biasing

Cited by 50 publications

References 8 publications

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

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