A normally-off GaN double-implanted vertical MOSFET (DMOSFET) with an atomic layer deposition (ALD)-Al2O3 gate dielectric film on a free-standing GaN substrate fabricated by triple ion implantation is presented. The DMOSFET was formed with Si ion implanted source regions in a Mg ion implanted p-type base with N ion implanted termination regions. A maximum drain current of 115 mA/mm, maximum transconductance of 19 mS/mm at a drain voltage of 15 V, and a threshold voltage of 3.6 V were obtained for the fabricated DMOSFET with a gate length of 0.4 μm with an estimated p-type base Mg surface concentration of 5 × 1018 cm−3. The difference between calculated and measured Vths could be due to the activation ratio of ion-implanted Mg as well as Fermi level pinning and the interface state density. On-resistance of 9.3 mΩ·cm2 estimated from the linear region was also attained. Blocking voltage at off-state was 213 V. The fully ion implanted GaN DMOSFET is a promising candidate for future high-voltage and high-power applications.
The differences in drain current and drain voltage (Id-Vd) characteristics of top and bottom contact organic thin film transistors (OTFTs) are analyzed by an OTFT devices simulator, which makes it possible to derive Id-Vd characteristics, potential distribution, and hole concentration distribution by solving Poisson’s equation and current continuity equation. It is found that the intrinsic characteristics of top contact devices are superior to those of the bottom contact ones, which is usually believed to be due to poor contact characteristics and poor semiconductor quality of bottom contact OTFTs. The mechanism behind the intrinsic characteristics differences is the deficiency of carriers at the source-channel interface, resulting to a very high potential drop, which the bottom contact devices suffer more. Remarkable improvements in drain current are expected by only inserting high carrier concentration region around the source/drain contact area, which totally eliminates the potential drop.
A bottom-gate, bottom-contact (BGBC) organic thin-film transistor (OTFT) with carrier-doped regions over source-drain electrodes was investigated. Device simulation with our originally developed device simulator demonstrates that heavily doped layers (p+ layers) on top of the source-drain contact region can compensate the deficiency of charge carriers at the source-channel interface during transistor operation, leading to the increase of the drain current and the apparent field-effect mobility. The phenomena expected with the device simulation were experimentally confirmed in typical BGBC pentacene thin-film transistors. The 5-nm-thick p+ layers, located 10 nm (or 20 nm) over the source-drain electrodes, were prepared by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane as an acceptor dopant. Since the molecular doping in this study can increase the drain current without positive shift of threshold voltage, p+ layers were formed precisely on top of the source-drain regions. This study shows that common inferior characteristics of bottom-contact OTFT devices mainly derive from the supply shortage of charge carriers to the channel region. The importance of reliable molecular doping techniques or heavily doped semiconductor materials for improving OTFT device performance is clearly suggested.
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