Calculation of the soft error rate of submicron CMOS logic circuits

Juhnke, T.; Klär, H.

doi:10.1109/4.391126

Cited by 39 publications

(15 citation statements)

References 8 publications

(2 reference statements)

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“…Technology trends will raise soft-error rates in microprocessors to levels that require changes to the design and implementation of future computer systems [12,17,23]. Detecting soft-errors in the processor's core logic presents a more difficult challenge than errors in storage or interconnect devices, which can be handled via error detecting and correcting codes.…”

Section: Introductionmentioning

confidence: 99%

Fingerprinting: bounding soft-error-detection latency and bandwidth

Smolens¹,

Kim²,

Falsafi³

et al. 2004

IEEE Micro

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Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a dual modular redundant (DMR) processor pair. Fingerprinting summarizes a processor's execution history in a hash-based signature; differences between two mirrored processors are exposed by comparing their fingerprints. Fingerprinting tightly bounds detection latency and greatly reduces the interprocessor communication bandwidth required for checking. This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection. The result of this study shows that fingerprinting is the only error detection mechanism that simultaneously allows high-error coverage, low error detection bandwidth, and high I/O performance.

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Section: Introductionmentioning

confidence: 99%

Fingerprinting: bounding soft-error-detection latency and bandwidth

Smolens¹,

Kim²,

Falsafi³

et al. 2004

IEEE Micro

View full text Add to dashboard Cite

show abstract

“…However, increasing levels of integration, diminishing node capacitance, and reduced noise margins have led researchers to forecast an exponential increase in the soft-error rate for unprotected logic and flip-flop circuits [10,19]. Recent work [9,14,22] advocates leveraging the inherent replication of processor cores in a CMP for soft-error tolerant redundant execution by pairing cores and checking their execution results.…”

Section: Introductionmentioning

confidence: 99%

Reunion: Complexity-Effective Multicore Redundancy

Smolens

Gold

Falsafi

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

114

110

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“…Furthermore, by waiting for outstanding transactions to complete, SafetyNet avoids checkpointing transient coherence states and in-flight messages. [28,36,49]). The fault may corrupt the message while it is stored in a switch buffer or by disrupting a switch's internal logic.…”

Section: Creating Consistent Checkpointsmentioning

confidence: 99%

SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery

Sorin

Martin

Hill

et al.

Proceedings 29th Annual International Symposium on Computer Architecture

167

206

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We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At an abstract level, SafetyNet logically maintains multiple, globally consistent checkpoints of the state of a shared memory multiprocessor (i.e., processors, memory, and coherence permissions), and it recovers to a pre-fault checkpoint of the system and re-executes if a fault is detected. SafetyNet efficiently coordinates checkpoints across the system in logical time and uses "logically atomic" coherence transactions to free checkpoints of transient coherence state. SafetyNet minimizes performance overhead by pipelining checkpoint validation with subsequent parallel execution.We illustrate SafetyNet avoiding system crashes due to either dropped coherence messages or the loss of an interconnection network switch (and its buffered messages). Using full-system simulation of a 16-way multiprocessor running commercial workloads, we find that SafetyNet (a) adds statistically insignificant runtime overhead in the common-case of fault-free execution, and (b) avoids a crash when tolerated faults occur. Architecture, 2002, May 2002 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Comments Copyright 2002 IEEE. Reprinted from Proceedings of the 29th Annual International Symposium on Computer

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Calculation of the soft error rate of submicron CMOS logic circuits

Cited by 39 publications

References 8 publications

Fingerprinting: bounding soft-error-detection latency and bandwidth

Fingerprinting: bounding soft-error-detection latency and bandwidth

Reunion: Complexity-Effective Multicore Redundancy

SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery

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