A single-poly EEPROM cell for embedded memory applications

Bartolomeo, Antonio Di; Rücker, H.; Schley, P.; Fox, A.; Lischke, Stefan; Na, Kee-Yeol

doi:10.1016/j.sse.2009.04.007

Cited by 39 publications

(31 citation statements)

References 14 publications

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“…Although this switching time is two or three orders of magnitude larger than that of commercial flash memory devices [21], it is similar to switching times of CNFETs with SiO 2 gate oxide reported by other groups [6,22]. We note that the switching time depends on the characteristic times of the charge traps in the gate oxide.…”

Section: Resultssupporting

confidence: 83%

Record Endurance for Single-Walled Carbon Nanotube–Based Memory Cell

et al. 2010

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We study memory devices consisting of single-walled carbon nanotube transistors with charge storage at the SiO2/nanotube interface. We show that this type of memory device is robust, withstanding over 105 operating cycles, with a current drive capability up to 10−6 A at 20 mV drain bias, thus competing with state-of-the-art Si-devices. We find that the device performance depends on temperature and pressure, while both endurance and data retention are improved in vacuum.

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Section: Resultssupporting

confidence: 83%

Record Endurance for Single-Walled Carbon Nanotube–Based Memory Cell

et al. 2010

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“…The combined effect of Joule heating and low pressure reduces/removes adsorbates and makes it possible to analyze the effect of intrinsic defects and traps only. The complete sweeping shows a right shift of the transfer curve, creating a hysteresis that can be explained in terms of negative charge trapping [25,56,62]. Hysteretic behavior can be analyzed by the hysteresis width H W (i.e., the difference of the gate voltage values corresponding to a channel current I ds = 0.1 nA).…”

Section: Transistor Characterizationmentioning

confidence: 99%

Nanotip Contacts for Electric Transport and Field Emission Characterization of Ultrathin MoS2 Flakes

et al. 2020

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We report a facile approach based on piezoelectric-driven nanotips inside a scanning electron microscope to contact and electrically characterize ultrathin MoS2 (molybdenum disulfide) flakes on a SiO2/Si (silicon dioxide/silicon) substrate. We apply such a method to analyze the electric transport and field emission properties of chemical vapor deposition-synthesized monolayer MoS2, used as the channel of back-gate field effect transistors. We study the effects of the gate-voltage range and sweeping time on the channel current and on its hysteretic behavior. We observe that the conduction of the MoS2 channel is affected by trap states. Moreover, we report a gate-controlled field emission current from the edge part of the MoS2 flake, evidencing a field enhancement factor of approximately 200 and a turn-on field of approximately 40 V / μ m at a cathode–anode separation distance of 900 nm .

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“…For example, in the MoS 2 ‐based FETs, charge traps may arise from the trapping centers at MoS 2 /SiO 2 interface, the adsorbates on the MoS 2 channel, or from intrinsic sulfur vacancies and other crystal defects . It is highly desirable to have a comprehensive understanding of the hysteresis and achieve a good control so that it can be either eliminated to avoid threshold voltage instability or conveniently exploited, for instance, into memory devices …”

Section: Introductionmentioning

confidence: 99%

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Bartolomeo

Pelella

Liu

et al. 2019

Adv Funct Materials

111

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Few-layer palladium diselenide (PdSe 2 ) field effect transistors are studied under external stimuli such as electrical and optical fields, electron irradiation, and gas pressure. The ambipolar conduction and hysteresis are observed in the transfer curves of the as-exfoliated and unprotected PdSe 2 material. The ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments are tuned. The prevailing p-type transport observed at atmospheric pressure is reversibly turned into a dominant n-type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristics of the device as required in highperformance logic circuits. The transistors are affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after an annealing of several minutes at room temperature. The work paves the way toward the exploitation of PdSe 2 in electronic devices by providing an experiment-based and deep understanding of charge transport in PdSe 2 transistors subjected to electrical stress and other external agents.

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A single-poly EEPROM cell for embedded memory applications

Cited by 39 publications

References 14 publications

Record Endurance for Single-Walled Carbon Nanotube–Based Memory Cell

Record Endurance for Single-Walled Carbon Nanotube–Based Memory Cell

Nanotip Contacts for Electric Transport and Field Emission Characterization of Ultrathin MoS2 Flakes

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

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