A single-chip concatenated FEC decoder

Luthi, D.A.; Mogre, A.; Ben-Efraim, Nadav; Gupta, Alok

doi:10.1109/cicc.1995.518187

Cited by 12 publications

(2 citation statements)

References 4 publications

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“…Most commercial products [4] still use the classical two-pointer trace-back scheme [5] and demand memory of size 4*K*N bits (K is the constraint length, N is the number of states). An alternative scheme using dual-port memory is proposed recently [6]. The memory requirement is halved while the number of trace-back multiplexers (N to 1) increase one to three.…”

Section: Introductionmentioning

confidence: 99%

FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

Sun¹,

Ding

2012

WET

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In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.

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Section: Introductionmentioning

confidence: 99%

FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

Sun¹,

Ding

2012

WET

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“…Each of the possible depuncturing sequences at each rate is tested as well as the 90 degree carrier phase ambiguity conditions. Conventional schemes re-encode the Viterbi decoder output and compare it with the depunctured symbol stream at the input to detect the in-sync condition [5]. Our device adopts a new scheme to find synchronization.…”

Section: Viterbi Decodermentioning

confidence: 99%

A single chip DVB receiver for variable-rate QPSK demodulation and forward error correction

Lee

Baek

Paff

et al.

Proceedings of CICC 97 - Custom Integrated Circuits Conference

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This paper describes a single chip DVB compliant receiver that integrates a variable rate QPSK demodulator with a Viterbi decoder, de-interleaver, and a Reed-Solomon decoder. Using a fixed rate sampling clock it handles continuously variable symbol rate from 1 Msps to 45 Msps. Careful floorplanning and flat place & route squeezed the 116,000 nand-cquivalcnt gatc design into an arca of 38.8mm2. It has been fabricated with a 0.5pm CMOS TLM process. It has been extensivcly tcsted in a real-world sct-up and proved fully functional. 11.7.4

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