FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

Sun, Yan; Ding, Zhizhong

doi:10.4236/wet.2012.33019

Cited by 9 publications

(3 citation statements)

References 9 publications

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“…The viterbi decoder is used to decode the output of the convolution encoder [11]. Block diagram of the viterbi decoder is shown in Figure11.…”

Section: Viterbi Decodermentioning

confidence: 99%

FPGA Implementation of MC-CDMA for High Security Applications

Ganesh¹,

Reddy²

2013

CVRJST

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The demand of wireless communications is increased in high speed, high security applications like missile communication, satellite communication etc. The communication with these features can be achieved by using different carrier modulation techniques like single carrier, multi carrier modulation etc. The multi carrier modulation with orthogonality of carriers provides high speed communication. This process is called Orthogonal Frequency Division Multiplexing (OFDM). The high speed and band width utilization can be achieved by using OFDM. The high security communication can be achieved by using coders and spreaders with different random generator sequences with the help of Spread Spectrum techniques. This can be done by using a method called Code Division Multiple Access (CDMA). The Multi Carrier CDMA is defined by adding the features of OFDM and CDMA and this is used for high speed and high secured communication system. The MC-CDMA uses convolution coder, viterbi decoder and spreader, de spreader etc to provide security. The MC-CDMA technique consists of a back to back connected transmitter and receiver with 8-point FFT/IFFT and QPSK modulation. This technique is designed by using Verilog HDL with Xilinx ISE Design suite 12.4 version tool. The design is implemented in Xilinx virtex-5 XUPV5LX110T FPGA board.

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“…The viterbi decoder is used to decode the output of the convolution encoder [11]. Block diagram of the viterbi decoder is shown in Figure11.…”

Section: Viterbi Decodermentioning

confidence: 99%

FPGA Implementation of MC-CDMA for High Security Applications

Ganesh¹,

Reddy²

2013

CVRJST

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“…[5] This paper is concerned with designing and implementing a convolutional encoder and a Viterbi decoder with interleaver/de-interleaver of DVB-T system, that are essential blocks in digital communication systems, using FPGA technology and comparing their results with that of the IPcore built-in design on Xilinx ISE (Integrated Software Environment) design Suite 12.4 program. There were many efforts to design and implement a convolutional encoder and Viterbi decoder with same constraint length(k=7) but without puncturing and with hard Viterbi decoder as in these papers [6], [7], [8], [9]. But this paper added the puncturing with code rate 2/3, soft Viterbi decoder and also their integration with inner interleaver and inner deinterleaver.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a standard inner convolutional codec for DVB-T system using VHDL

Hussein

Zekry²,

Baioumy³

et al. 2017

IJET

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Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors. This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.

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“…Parallel decode complex degree is and restrain length index relation. The most important decode method of convolution code is Viterbi decode, in the decoding process, not only from the current moment received code group extracted decoding information, but also to use before or after each time of received code extracting relevant information (Sun & Ding, 2012;Niu & Ma, 2011;Cholan, 2012).…”

Section: Introductionmentioning

confidence: 99%

The Design of Efficient Viterbi Decoder and Realization by FPGA

Liu¹,

Yang²,

Chen³

2012

MAS

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Convolution code is a kind of widely used error-correcting codes in the error control field, in order to solve the Viterbi decoding of higher complex degree and lower speed etc. problem, a kind of efficient and reliable Viterbi decode method has been put forward specially. Firstly, the principle of Viterbi decode has been introduced by detail; Secondly, in order to improve the parallel decoding speed, Viterbi decoding algorithm is improved; And then, according to the improved algorithm to achieve high speed and parallel Viterbi decoding method, which is realized easily by FPGA; Finally, the function simulation and test for (2, 1, 7) convolution code has been carried out. The experimental results show that: when the system clock is 64 MHz, eventually the decoding rate of not less than 16 Mbps, improved Viterbi decoding algorithm has lower complexity, improved Viterbi decoding efficiency.

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FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

Cited by 9 publications

References 9 publications

FPGA Implementation of MC-CDMA for High Security Applications

FPGA Implementation of MC-CDMA for High Security Applications

Implementation of a standard inner convolutional codec for DVB-T system using VHDL

The Design of Efficient Viterbi Decoder and Realization by FPGA

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