A single chip DVB receiver for variable-rate QPSK demodulation and forward error correction

Abstract

This paper describes a single chip DVB compliant receiver that integrates a variable rate QPSK demodulator with a Viterbi decoder, de-interleaver, and a Reed-Solomon decoder. Using a fixed rate sampling clock it handles continuously variable symbol rate from 1 Msps to 45 Msps. Careful floorplanning and flat place & route squeezed the 116,000 nand-cquivalcnt gatc design into an arca of 38.8mm2. It has been fabricated with a 0.5pm CMOS TLM process. It has been extensivcly tcsted in a real-world sct-up and proved fully functional. 11.7.4