A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

Kanda, Kensuke; Tamura, Hirotaka; Yamamoto, Takuji; Matsubara, S.; Kibune, Masaya; Doi, Yoshihiro; Shibasaki, Takayuki; Tzartzanis, N.; Kristensson, Anders; Parikh, Samir; Ide, Satoshi; Tsunoda, Yukito; Yamabana, T.; Sugawara, Mariko; Kuwata, N.; Ikeuchi, Tadashi; Ogawa, J.; Walker, Bill

doi:10.1109/jssc.2009.2031030

Cited by 22 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the widely used half-rate architecture shown in Fig. 1, the delay difference between the data and the clock tree buffer paths (t 1 -t 2 ) may fluctuate beyond 1 unit interval (UI) at high-speed rate under different PVT corners [12], thus causing setup/hold timing violations for the high-speed latches. To solve this problem, reference [13] additional calibration loop to guarantee the timing constraint between the data and the clock.…”

Section: Introductionmentioning

confidence: 99%

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

Lv¹,

Zheng²,

Zhao³

et al. 2018

JSTS

View full text Add to dashboard Cite

A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS http://researchonline.ljmu.ac.uk/8698/ Article LJMU has developed LJMU Research Online for users to access the research output of the University more effectively.Abstract-This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-tozero (NRZ) modulation with a multiplexer (MUX)based two-tap feed-forward equalizer (FFE). An edgeacceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. Index Terms-Four-level pulse amplitude modulation (PAM4), non-return-to-zero (NRZ), edge-acceleration technique, linearity optimization, dual-mode wireline transmitter

show abstract

Section: Introductionmentioning

confidence: 99%

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

Lv¹,

Zheng²,

Zhao³

et al. 2018

JSTS

View full text Add to dashboard Cite

show abstract

“…For high-speed data processing, the current-mode-logic (CML) technique is used to realize the time-decision latch and the data-arrangement multiplexer [5]- [7]. The two level series-gated CML schematics selects the two-phase operation and cooperates with the series inductor-resistor load to extend the CML bandwidth [8].…”

Section: Introductionmentioning

confidence: 99%

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

Chen

Chang

2015

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.

show abstract

“…The fastest published SST drivers [3][4][5] accomplish low power consumption and low jitter, and operate in the data rate range adequate for the 28Gb/s standard generation (OIF-CEI-25G-LR, OIF-CEI-28G-VSR). To continue to exploit the high power efficiency and high voltage swing in the 50Gb/s generation applications and incoming standards (OIF-CEI-56G-VSR), SST drivers should be demonstrated that operate in the range of the fastest CML drivers [6,7,8] with sufficient output swing and return loss performance. In this paper we demonstrate a 2:1 multiplexer and a SST driver with such features by using a simple static CMOS design style without the passive components except in the termination, allowing for compact layout and high frequency of operation.…”

Section: Introductionmentioning

confidence: 99%