A silicon carbide self-aligned and ion implanted static induction transistor (SAI-SIT) for 150 watt S-Band operation

Knight, Thomas J.; Clarke, R.C.; Barron, R.R.; Ostop, J.; Morick, B.A.; Gigante, J. R.; Malkowski, W. J.; Morse, A.W.; DeSalvo, G.; Petrosky, K.J.; Curtice, W.R.

doi:10.1109/drc.2002.1029586

Cited by 6 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The depth of a SiC commercial ion implantation event is less than 1 μm. However, the actual gate length controlling the channel is ∼ 0.5 μm due to the lateral implantation straggle [13], [14]. For a channel (gate) length of 0.5 μm and channel dopings in the 1 × 10 16 to 6 × 10 16 cm −3 range, channel widths and ON-state resistances were calculated for 1200-V N-OFF blocking.…”

Section: Resultsmentioning

confidence: 99%

Investigation of the Suitability of 1200-V Normally-Off Recessed-Implanted-Gate SiC VJFETs for Efficient Power-Switching Applications

Veliadis

Hearne

Stewart

et al. 2009

IEEE Electron Device Lett.

View full text Add to dashboard Cite

A recessed-implanted-gate (RIG) 1290-V normallyoff (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFET's ON-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high ON-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific ON-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mΩ · cm 2 , has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.Index Terms-Current gain, enhancement mode, JFET, normally-off (N-OFF), vertical channel, 1200 V, 4H-SiC.

show abstract

Section: Resultsmentioning

confidence: 99%