We report the design and test of reciprocal quantum logic shift-register yield vehicles consisting of up to 72 800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 μm. The largest individual circuits with 40 400 junctions indicate large operating margins of ±20% on ac clock amplitude. In one case the data were reproducible to the accuracy of the measurement, ±1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK s−1 in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.

Recommended by Peter FriedrichsSiC VJFETs are excellent candidates for reliable high-power/temperature switching as they only use pn junctions in the active device area where the high-electric fields occur. VJFETs do not suffer from forward voltage degradation, exhibit excellent short-circuit performance, and operate at 300 • C. 0.19 cm 2 1200 V normally-on and 0.15 cm 2 low-voltage normally-off VJFETs were fabricated. The 1200-V VJFET outputs 53 A with a forward drain voltage drop of 2 V and a specific onstate resistance of 5.4 mΩ cm 2 . The low-voltage VJFET outputs 28 A with a forward drain voltage drop of 3.3 V and a specific onstate resistance of 15 mΩ cm 2 . The 1200-V SiC VJFET was connected in the cascode configuration with two Si MOSFETs and with a low-voltage SiC VJFET to form normally-off power switches. At a forward drain voltage drop of 2.2 V, the SiC/MOSFETs cascode switch outputs 33 A. The all-SiC cascode switch outputs 24 A at a voltage drop of 4.7 V.

No abstract

Electron-hole recombination-induced stacking faults have been shown to degrade the I-V characteristics of SiC power p-n diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effect of bipolar gate-to-drain current on vertical-channel JFETs. The devices have n- drift epitaxial layers of 12-μm and 100-μm thicknesses, and were stressed at a fixed gate-to-drain current density of 100 A/cm2 for 500 hrs and 5 hrs, respectively. Significant gate-to-drain and on-state conduction current degradations were observed after stressing the 100-μm drift VJFET. Annealing at 350°C reverses the stress induced degradations. After 500 hours of stressing, the gate-to-source, gate-to-drain, and blocking voltage characteristics of the 12-μm VJFET remain unaffected. However, the on-state drain current was 79% of its pre-stress value. Annealing at 350°C has no impact on the post-stress on-state drain current of the 12-μm VJFET. This leads us to attribute the degradation to a “burn-in” effect.

High-voltage normally-on VJFETs of 0.19 cm2 and 0.096 cm2 areas were manufactured in seven photolithographic levels with no epitaxial regrowth and a single ion implantation event. A self aligned guard ring structure provided edge termination. At a gate bias of -36 V the 0.096 cm2 VJFET blocks 1980 V, which corresponds to 91% of the 12 μm drift layer’s avalanche breakdown voltage limit. It outputs 25 A at a forward drain voltage drop of 2 V (368 A/cm2, 735 W/cm2) and a gate current of 4 mA. The specific on-resistance is 5.4 mΩ cm2. The 0.19 cm2 VJFET blocks 1200 V at a gate bias of -26 V. It outputs 54 A at a forward drain voltage drop of 2 V (378 A/cm2, 755 W/cm2) and a gate current of 12 mA, with a specific on-resistance of 5.6 mΩ cm2. The VJFETs demonstrated low gate-to-source leakage currents with sharp onsets of avalanche breakdown.