Large Area Silicon Carbide Vertical JFETs for 1200 V Cascode Switch Operation

Veliadis, Victor; McNutt, Ty; Snook, Megan; Hearne, Harold; Potyraj, Paul; Junghans, Jeremy; Scozzie, Charles

doi:10.1155/2008/523721

Cited by 21 publications

(12 citation statements)

References 14 publications

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“…A high-voltage, low on-state resistance N-on SiC JFET can be connected in a hybrid cascode configuration with a low-voltage N-off Si MOSFET or a low-voltage N-off JFET to create a N-off power switch with a control characteristic similar to a Si MOSFET or IGBT [8][9][10][11][12][13]. However, the hybrid cascode solutions suffer from parasitic inductances, capacitance miss-match, and related instabilities due to the necessity of connecting separate commercially available device chips.…”

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confidence: 99%

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Malhan

Bakowski

Takeuchi

et al. 2009

Physica Status Solidi (a)

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This paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures. Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations. The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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confidence: 99%

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Malhan

Bakowski

Takeuchi

et al. 2009

Physica Status Solidi (a)

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“…Furthermore, in recent times, the price of the SiC devices has dropped markedly so that they are more and more competitive with respect to the conventional Si devices. A cross examination of the main characteristics of Si and SiC devices is reported in [5][6][7][8][9][10][11].…”

Section: Sic Devicesmentioning

confidence: 99%

“…Recent advancements in wide bandgap (WBG) devices fabrication, especially for the silicon carbide (SiC) devices, have led to the development of high-voltage power transistors with short switching time and low conduction resistance [5,6]. Consequently, appreciable improvement in the propulsion inverter efficiency is expected if built up with SiC devices, such as the SiC MOSFETs, instead of with silicon (Si) IGBTs, owing to the reduction of both switching and conduction losses [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Quantitative Analysis of Efficiency Improvement of a Propulsion Drive by Using SiC Devices: A Case of Study

Kumar¹,

Bertoluzzo

Buja

et al. 2017

Advances in Power Electronics

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One of the emerging research topics in the propulsion drive of the electric vehicles is the improvement in the efficiency of its component parts, namely, the propulsion motor and the associated inverter. This paper is focused on the efficiency of the inverter and analyzes the improvement that follows from the replacement of the silicon (Si) IGBT devices with silicon carbide (SiC) MOSFETs. To this end, the paper starts by deriving the voltage-current solicitations of the inverter over the working torquespeed plane of the propulsion motor. Then, a proper model of the power losses in the inverter over a supply period of the motor is formulated for the two types of device, including the integrated freewheeling diode. By putting together the voltage-current solicitations and the device power losses, the efficiency maps of the Si IGBT and SiC MOSFET inverters are calculated and compared over the torque-speed plane. The results for the Si IGBT inverter are supported by measurements executed on a marketed C-segment compact electric car, while the SiC MOSFET loss model is validated by an on-purpose built test bench. Finally, the overall efficiency of the propulsion drive is calculated by accounting for the motor efficiency. Main outcomes of the paper is a quantitative evaluation of both the improvement in the efficiency achievable with the SiC MOSFETs and the ensuing increase in the electric car range.

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“…It can be utilized as a normally-ON power switch or connected with a low-voltage N-OFF transistor to form an N-OFF cascode power switch [16]. As the thick drift layer of the 9-kV VJFET is the primary resistance contributor, connecting with low-voltage transistors in the cascode configuration has a negligible impact on overall resistance [17].…”

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A 9-kV Normally-on Vertical-Channel SiC JFET for Unipolar Operation

Veliadis

Stewart

Hearne

et al. 2010

IEEE Electron Device Lett.

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A normally-ON 9-kV (at 0.1-mA/cm 2 drain leakage) 1.52 × 10 −3 -cm 2 active-area vertical-channel SiC JFET (VJFET) is fabricated with no e-beam lithography, no epitaxial regrowth, and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped extension. The VJFET exhibits low leakage currents and a sharp onset of gate-voltage breakdown occurring at 80 V. To lower resistance, the VJFET is designed to be very normally-ON, which minimizes the channel resistance contribution. At a gate bias of 0 V, the VJFET's drain current is 73 mA with a forward drain voltage drop of 5 V (240 W/cm 2 ), a specific ON-state resistance of 104 mΩ · cm 2 , and a current gain of I D /I G = 6.4 × 10 6 . Operating at a unipolar gate bias of 2.5 V lowers the ON-state resistance to 96 mΩ · cm 2 and raises the drain-current output to 79.3 mA, with the current gain being relatively high at I D /I G = 2346. Thus, this 9-kV VJFET is capable of efficient power switching operation with high current gain at a low unipolar resistance.

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Large Area Silicon Carbide Vertical JFETs for 1200 V Cascode Switch Operation

Cited by 21 publications

References 14 publications

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Quantitative Analysis of Efficiency Improvement of a Propulsion Drive by Using SiC Devices: A Case of Study

A 9-kV Normally-on Vertical-Channel SiC JFET for Unipolar Operation

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