Investigation of the Suitability of 1200-V Normally-Off Recessed-Implanted-Gate SiC VJFETs for Efficient Power-Switching Applications

Abstract

A recessed-implanted-gate (RIG) 1290-V normallyoff (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFET's ON-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high ON-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific ON-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mΩ · cm 2 , has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.Index Terms-Current gain, enhancement mode, JFET, normally-off (N-OFF), vertical channel, 1200 V, 4H-SiC.

A 9-kV Normally-on Vertical-Channel SiC JFET for Unipolar Operation

“…Selfaligned high-temperature Al implantation reaches a depth of 0.9 μm. However, the actual gate length controlling the channel is 0.5 μm due to the inherent lateral straggle of ion implantation [14], [19]. After the edge termination implantations, hightemperature thermal annealing in the presence of a protective cap layer activates the implanted atoms and recrystallizes the material.…”

“…At a gate bias of V GS = 2.5 V, the unipolar ON prohibitively increases by more than an order of magnitude to about 1400 mΩ · cm 2 [6]. Although the ON-state resistance of high-voltage VJFETs can be greatly reduced by turning on the gate junction [13], significant bipolar current injection occurs into the channel, and the current gain decreases as the gate voltage increases in excess of its built-in potential value [12], [14]. Consequently, a larger gate-drive physical size with correspondingly increased power consumption is required.…”

Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts

“…In recent years a number of SiC JFET designs have been developed. Significant progress has been made in the development of both normally-on and normally-off high-power trenched and implanted vertical JFETs (TI-VJFETs) [1,2]. The gate regions of these devices have been fabricated by forming source strip-like mesa-structures followed by the ion implantation into trenches between them to form p-doped gate regions.…”

Performance of a 600-V, 30-A, Bi-Directional Silicon Carbide Solid-State Circuit Breaker

“…1 BDSSCB tests using two 0.1-cm 2 devices showed symmetric 600-V blocking and 10-A conduction using a 0-V ON-state gate bias, with no formation of bipolar gate current. 3,4 For a wide range of BDSSCB current ratings, parallel sets of common-source connected devices are needed. The positive temperature coefficient of ON-state resistance and low gate charge indicate that parallel connected JFETs will share current well during both steady-state conduction and device transitions.…”