A scheme for enabling the ultimate speed of threshold switching in phase change memory devices

Abstract

Phase change materials exhibit threshold switching (TS) that establishes electrical conduction through amorphous material followed by Joule heating leading to its crystallization (set). However, achieving picosecond TS is one of the key challenges for realizing non-volatile memory operations closer to the speed of computing. Here, we present a trajectory map for enabling picosecond TS on the basis of exhaustive experimental results of voltage-dependent transient characteristics of Ge2Sb2Te5 phase-change memory (PCM) devices. We demonstrate strikingly faster switching, revealing an extraordinarily low delay time of less than 50 ps for an over-voltage equal to twice the threshold voltage. Moreover, a constant device current during the delay time validates the electronic nature of TS. This trajectory map will be useful for designing PCM device with SRAM-like speed.

Time-Domain Analysis of Chalcogenide Threshold Switching: From ns to ps Scale

“…The voltage pulse generated by experimental equipments varies from zero to its maximum programmed value in a finite time which, at present, can be as short as few ns [23,25]. Thus, every "real" voltage pulse contains, de facto, ramps with rise and fall times of finite duration; this implies the existence of a time transient of the electrical response of the device, during which the internal electric field increases or decreases.…”

“…Despite efforts to decrease t d with different strategies, so far it has been difficult to obtain values below 1 ns [23]. Thus, achieving sub ns threshold-switching times for nanoscale devices is a goal of both scientific and technological relevance [23,25].…”

“…This concept is pushed even further in a recent paper by Saxena and coworkers [25], where it is shown that delay times in the ps scale can be obtained in GST-225 cells by means of an appropriate design of both the experimental apparatus and the external voltage applied to the cell. In particular, the Authors measured delay times shorter than 50 ps for a voltage equal to twice the threshold voltage measured in static conditions for the same material, proving that PCM memory devices can reach SRAM-like speeds.…”

“…A numerical solution of the constitutive equations of the model for a time-dependent bias makes it possible to test to what extent the threshold voltage depends upon the microscopic characteristic times that regulate the field-to-carrier energy transfer; this transfer is in fact responsible for the carrier heating which, in turn, produces the threshold switching. Furthermore, the analysis is extended to include the effect of the external circuit on the electrical switching, with reference to the optimised electrical set up configurations recently used by experimental groups [25].…”

“…Dynamic and static models for the OTS device have been tested in view of their possible implementation into a device simulation framework. Section 3 contains our results and their critical analysis: first, parasitic effects are neglected; the ideal cases of a voltage step (Section 3.1) and of voltage trapezoidal profiles, similar to those reported in [25], are considered with the purpose of evaluating the delay time of the OTS device (Section 3.2); then, the more realistic condition of a voltage trapezoidal profile applied to a device in presence of parasitic effects is studied (Section 3.3). Finally, Section 4 summarises the main achievements of the analysis, and provides some comments about possible developments of the present approach.…”