A scalable ODC-based algorithm for RTL insertion of gated clocks

Babighian, P.; Benini, Luca; Macii, E.

doi:10.1109/date.2004.1268895

Cited by 15 publications

(13 citation statements)

References 7 publications

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“…For example, the methods described in [3,5] identify ODCs or STCs and transform them into clock-gating conditions. Static methods face a trade-off between scalability and accuracy.…”

Section: Related Workmentioning

confidence: 99%

“…The FSManalysis technique of [5] requires extensive logic analysis and does not scale well, which limits its applicability to fairly small design blocks. In contrast, the method of [3] achieves scalability by limiting its analysis to unobservability conditions of a certain kind (those that can be obtained from analysis of steering modules), thereby missing many potentially useful clock-gating opportunities.…”

Section: Related Workmentioning

confidence: 99%

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Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

Wiener

Kamhi

Vardi

2009

Lecture Notes in Computer Science

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Abstract. In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of a clock net's power) on industrial micro-processor designs.

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“…For example, the methods described in [3,5] identify ODCs or STCs and transform them into clock-gating conditions. Static methods face a trade-off between scalability and accuracy.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

Wiener

Kamhi

Vardi

2009

Lecture Notes in Computer Science

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“…Various power reduction techniques have been proposed and implemented in all levels of the computing system, from software and architecture levels [6] to circuit levels [7]. At the circuit level, many clock-gating and power-gating techniques had been proposed [3], [8]- [9]. Clock-gating could be classied into two main approaches [8].…”

Section: Introductionmentioning

confidence: 99%

“…Logic synthesis is interested in optimizing circuits in terms of area [1], time [2] and/or power [3]. Power consumption is one of the major considerations in modern chip design.…”

Section: Introductionmentioning

confidence: 99%

Novel SAT-based invariant-directed low-power synthesis

Elbayoumi

Hsiao

ElNainay

2015

Sixteenth International Symposium on Quality Electronic Design

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Dynamic power consumption is a critical concern in the design of both high performance and low-power circuits. Clock-gating is one of the most efficient and prominent approaches to reduce dynamic power. In this paper, (1) we propose the first scalable SAT-based approaches for Observability Dont Care (ODC) based clock gating; (2) we intelligently choose those inductive invariants candidates such that their validation will benefit clock-gating-based low-power design. Our approach shows an average 23.2% reduction in dynamic power with an average 9.5% increase in area.

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“…In this paper, we propose architectures for improving the power and performance of an embedded processor. The architectures are the branch predictor, 4-way set-associative cache architecture for performance improvement and clockgating logics using observability don't care (ODC) conditions for a low-power embedded processor [7].…”

mentioning

confidence: 99%

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

Jung¹,

Jin²,

Ryoo

2012

Journal of information and communication convergence engineerin

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AS the densities of very-large-scale integration (VLSI) circuits and process technologies have been developed quickly in the past several years, performances of embedded processors have been greatly improved and used in many embedded systems including network systems, communication systems, and household appliances. Various technical approaches to performance have been applied during the process implementation of these systems. This is attributed to the development of embedded processors. It is necessary to consider performance improvement and power consumption during a processor design. Although most processors use a delayed branch for normal pipeline operations, pipeline operation delay caused by a delayed branch has become a serious obstacle for improving performance [1][2][3][4].Caches have become the most basic and the most important elements determining the performance of high performance microprocessors with unsatisfyingly limited memory bandwidth provided by the systems. In addition, most of the dynamic power of a processor is dissipated on the clock and data-path related circuits. This is a central part of a low-power design to reduce the dynamic power dissipated on high-activity lines [5,6]. In this paper, we propose architectures for improving the power and performance of an embedded processor. The architectures are the branch predictor, 4-way set-associative cache architecture for performance improvement and clockgating logics using observability don't care (ODC) conditions for a low-power embedded processor [7].The rest of this paper is organized as follows. Section II briefly reviews the OpenRISC core. In section III, we present the architecture of the 4-way set-associative cache. Section IV shows the dynamic branch prediction algorithm that uses branch target buffer (BTB). Section V presents the AbstractThis paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don't care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 μm technology library is reduced by 16%.

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A scalable ODC-based algorithm for RTL insertion of gated clocks

Cited by 15 publications

References 7 publications

Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

Novel SAT-based invariant-directed low-power synthesis

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

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