Abstract. In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of a clock net's power) on industrial micro-processor designs.
Power dissipation is a major concern in modern VLSI circuit design. Clock gating is a technique which allows substantial dynamic power reduction on the clock network by halting it in parts of the design which are not active. In this work we introduce an algorithm to detect general invariants so as to reveal logical behavior that will allow efficient clock gating in the design. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. We extract and compile gating conditions by using the circuit's existing logic as building blocks by analyzing power simulation benchmarks trace data. Experimental results show the ability to cope with the size of industrial RTL circuit designs and the ability to learn clock gating Boolean functions from dynamic simulation traces. vi
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