Intelligate: Scalable Dynamic Invariant Learning for Power Reduction

Abstract

Abstract. In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of a clock net's power) on industrial micro-processor designs.

SAT-based synthesis of clock gating functions using 3-valued abstraction

“…We show as an example one of the simpler algorithms and note that the results of this paper are equally applicable to all other functional analysis algorithms, e.g. [4], [24], [12], [23], [5], [14].…”

“…By avoiding functional analysis these methods are usually scalable enough to handle large designs. Some methods produce candidates for clock gating by examining simulation traces [24], [12]. Since simulation can provide only a partial information on the behavior of the design, these candidates still need to be proven for correctness in order to be considered valid.…”

“…Combinational clock gating algorithms disable the clock of latches whose outputs are not about to change ( [24], [12], [23], [6], [13]). Sequential clock gating alters the behavior of latches without affecting design functionality, e.g.…”

Novel SAT-based invariant-directed low-power synthesis

“…Various power reduction techniques have been proposed and implemented in all levels of the computing system, from software and architecture levels [6] to circuit levels [7]. At the circuit level, many clock-gating and power-gating techniques had been proposed [3], [8]- [9]. Clock-gating could be classied into two main approaches [8].…”

“…At the circuit level, many clock-gating and power-gating techniques had been proposed [3], [8]- [9]. Clock-gating could be classied into two main approaches [8]. In one approach, Observability Dont Cares (ODCs) are used to gate state elements that are not observed by the next-state or circuit outputs [3].…”