We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.
Recently, a network defense simulator becomes essential in studying cyber incidents as the cyber terror becomes more and more interesting. The network defense simulator is a tool to estimate damages and effectiveness of a defense mechanism by modeling network intrusions and defense mechanisms. Using this tool, users can find efficient ways of preventing cyber terror and recovering from the damage. Previous simulators start the simulation after entire scenario has prepared and been loaded onto simulation engine. However, in this way it is not suitable to model human judgement and behavior, therefore it is impossible to simulate the real cyber terror very well. In this paper, we have added a dynamic simulation component to our previous network defense simulator. This component improves accuracy of modeling of network intrusions and defense behaviors. We have also proposed modified architecture of the simulator system. Finally we have verified correctness of simulation results by simulating slammer worm.
In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.
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