A Scalable, Non-blocking Approach to Transactional Memory

Chafi, Hassan; Casper, Jared; Carlstrom, Brian D.; McDonald, Austen; Minh, Chi Cao; Baek, Woongki; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1109/hpca.2007.346189

Cited by 123 publications

(160 citation statements)

References 28 publications

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“…All writes are then committed through the "channel" created, after which the bus is unlocked with another LOCK BUS message, resuming normal operation. More efficient schemes can be supported in the future to enable parallel commits [3].…”

Section: Bus Extensionsmentioning

confidence: 99%

“…Transactional Memory can be implemented in hardware (HTM) [3], [16], which is fast but resourcebounded while usually requiring changes to the caches and the Instruction Set Architecture (ISA), or software (STM) [9] which can be flexible, run on off-the-shelf hardware, albeit at the expense of lower performance. To have the best of two worlds, there are intermediate Hybrid TM (HyTM) proposals where transactions first attempt to run on hardware, but are backed off to SW when HW resources are exceeded, and Hardwareassisted STM (HaSTM) which aims to accelerate a software-controlled TM implementation by architectural means [7], [2].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Sönmez

Arcas

Pflucker

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

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Section: Bus Extensionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Sönmez

Arcas

Pflucker

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

View full text Add to dashboard Cite

show abstract

“…When a conflict is detected, the transaction does a rollback. The snooping version of TCC is modified in [16] to a scalable version based on a directory protocol solution.…”

Section: Transactional Coherence and Consistency Tccmentioning

confidence: 99%

“…Transactional Coherence and Consistency (TCC) [41,39,40,67,16] is based on the observation that for well synchronized programs, coherence and consistency are only needed to be maintained at synchronization points. TCC is proposed as a new shared memory model where atomic transactions always are the basic units of work and communication, as well as for memory coherence and consistency.…”

Section: Transactional Coherence and Consistency Tccmentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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“…The Transactional Memory [10], [5], [14], [12], [7] is a technology where programmers just need to wrap a portion of the code in what is known as a transaction. It is then the responsibility of the TM framework to enforce Atomicity and Isolation properties to guarantee correctness.…”

Section: Introductionmentioning

confidence: 99%

Clock gate on abort: Towards energy-efficient hardware Transactional Memory

Sanyal

Roy²,

Cristal

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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Abstract-Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally [4].We are proposing to turn-off a processor dynamically by gating all its clocks, whenever any transaction running in it is aborted. We have described a novel protocol which can be used in the Scalable-TCC like Hardware Transactional Memory systems. Also in the protocol we are proposing a gating-aware contention management policy to set the duration of the clock gating period precisely so that both performance and energy can be improved.With our proposal we got an average 19% savings in the total consumed energy and even an average speed-up of 4%.

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A Scalable, Non-blocking Approach to Transactional Memory

Cited by 123 publications

References 28 publications

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Transactional memory

Clock gate on abort: Towards energy-efficient hardware Transactional Memory

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