Clock gate on abort: Towards energy-efficient hardware Transactional Memory

Abstract

Abstract-Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally [4].We are proposing to turn-off a processor dynamically by gating all its clocks, whenever any transaction running in it is aborted. We have described a novel protocol which can be used in the Scalable-TCC like Hardware Transactional Memory systems. Also in the protocol we are proposing a gating-aware contention management policy to set the duration of the clock gating period precisely so that both performance and energy can be improved.With our proposal we got an average 19% savings in the total consumed energy and even an average speed-up of 4%.

Green-CM: Energy Efficient Contention Management for Transactional Memory

“…Indeed, the few existing works on TM that tried to optimize both energy and performance were mainly revolving around energy efficient hardware implementations of TM [8], [21]- [23].…”

“…Sanyal et al [21] pursue energy efficiency in hardware transactional memory by clock gating processors upon abort of a transaction. Baldassin et al [9] adopted a similar idea, although implemented at the software level and integrated with the CM module: using DVFS to lower the frequency of cores upon abort and during the (exponential) back-off phase.…”

Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling

“…The first comparison is based on work done by Sanyal et al [26]. When a transaction is aborted by a committing transaction, the clocks of the aborted processor are halted and remain so until a local timer expires.…”

“…However, their work relied on four non-contentious SPLASH-2 benchmarks and one in-house microbenchmark, making it difficult to draw any meaningful conclusions. Using an analytical model to estimate the additional power for an Alpha 21264, Sanyal et al [26] proposed a technique for clock gating on an abort using TCC. Neither of these proposals exploit the feedback inherently available in transactional memory like the scheduler proposed by Yoo and Lee [34] who proposed an adaptive scheduler using parallelism feedback and showed speedups of almost 2x for his selected benchmarks.…”

“…First, it abstracts the differences in the hardware, allowing for an almost direct comparison of power for different conflict detection and version management schemes. Secondly, the proposed method does not assume that contentious transactions should be serialized like [21] and is much less complicated than [26]. …”